RE: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

RE: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[rufus]

On 19 Apr 2021 02:33, Jim Wilson wrote:
> Everything was written by SiFive and Andes employees, and both have
> corporate assignments that include gdb.

Behalf of Andes tech, I am OK with this patch set.
Thanks, Jim.
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[PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

These are mostly patches extracted from riscv-gnu-toolchain with minor
changes to apply to current FSF GDB sim.  I was careful to maintain the
original author info, and the original commit logs when reasonable.
There are also a few extra patches from me added in, as I noticed some
problems when reviewing the patches, and debugging issues.  Note that
Kito and Monk were at Andes when they wrote these patches, and are now
at SiFive.  So this is mostly Andes work, and they should get credit
for this work.  I kept their original email addresses even though they
won't work anymore.  We will need permission from Andes to merge the
patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
from Palmer and myself were written at SiFive.

I tested this with a gcc make check using riscv-gnu-toolchain and pulling
in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
matches the old simulator port in riscv-gnu-toolchain.  I did have one
problem with the GNUC code in mulhu function producing the wrong result,
but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
this is still broken with newer gcc versions I will take another look at
that.

This code can probably use some cleanup.  I'd like to see the extensions
in canonical arch order for instance.  But dealing with this many patches
is unwieldy, and I wanted to retain the original authorship for the
patches, so I'd rather do cleanup work as follow on patches.

Jim

Jim Wilson (6):
  RISC-V sim: Fix fence.i.
  RISC-V sim: More atomic fixes.
  RISC-V sim: Fix ebreak, part 2.
  RISC-V sim: Fix mingw builds.
  RISC-V sim: Support compressed FP instructions.
  RISC-V sim: Add zicsr support.

Kito Cheng (9):
  RISC-V sim: Atomic fixes.
  RISC-V sim: Fix syscall fallback.
  RISC-V sim: Add csrr*i instructions.
  RISC-V sim: Improve cycle and instret counts.
  RISC-V sim: Check sbrk argument.
  RISC-V sim: Improve branch tracing.
  RISC-V sim: Improve tracing for slt* instructions.
  RISC-V sim: Set brk to _end if possible.
  RISC-V sim: Fix divw and remw.

Kuan-Lin Chen (5):
  RISC-V sim: Fix stack pointer alignment.
  RISC-V sim: Add link syscall support.
  RISC-V sim: Add brk syscall.
  RISC-V sim: Add gettimeofday.
  RISC-V sim: Fix tracing typo.

Monk Chiang (3):
  RISC-V: Add fp support.
  RISC-V sim: Fix ebreak.
  RISC-V sim: Add compressed support.

Palmer Dabbelt (1):
  RISC-V sim: Fix for jalr.

 sim/riscv/interp.c   |   45 ++
 sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
 sim/riscv/sim-main.h |   16 +-
 3 files changed, 1733 insertions(+), 118 deletions(-)

-- 
2.7.4

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger via Gdb-patches]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> These are mostly patches extracted from riscv-gnu-toolchain with minor
> changes to apply to current FSF GDB sim.  I was careful to maintain the
> original author info, and the original commit logs when reasonable.
> There are also a few extra patches from me added in, as I noticed some
> problems when reviewing the patches, and debugging issues.  Note that
> Kito and Monk were at Andes when they wrote these patches, and are now
> at SiFive.  So this is mostly Andes work, and they should get credit
> for this work.  I kept their original email addresses even though they
> won't work anymore.  We will need permission from Andes to merge the
> patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> from Palmer and myself were written at SiFive.

can you summarize author & company FSF assignments ?  we'd need those before
we could/should review anything from them.
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sat, Apr 17, 2021 at 1:38 PM Mike Frysinger <vapier@gentoo.org> wrote:

> can you summarize author & company FSF assignments ?  we'd need those
> before
> we could/should review anything from them.
>

Everything was written by SiFive and Andes employees, and both have
corporate assignments that include gdb.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger via Gdb-patches]

On 18 Apr 2021 19:33, Jim Wilson wrote:
> On Sat, Apr 17, 2021 at 1:38 PM Mike Frysinger <vapier@gentoo.org> wrote:
> > can you summarize author & company FSF assignments ?  we'd need those
> > before
> > we could/should review anything from them.
> 
> Everything was written by SiFive and Andes employees, and both have
> corporate assignments that include gdb.

i don't follow this part then of your e-mail:
> We will need permission from Andes to merge the patches into FSF GDB.

if they have assignments in place, and the patches were released publicly,
then what is left ?
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:23 PM Mike Frysinger <vapier@gentoo.org> wrote:

> i don't follow this part then of your e-mail:
> > We will need permission from Andes to merge the patches into FSF GDB.
>

Just because Andes has an assignment, doesn't mean that the code that they
write automatically becomes owned by the FSF.  They have to agree to the
copyright transfer.  This is implied when you submit a patch.  But this is
not implied if someone other than the author submits the patch.  So,
technically, I need permission from the original author (Andes) to submit
the code on their behalf.  Kuan-Lin has given that permission.  It is very
rare for this technicality to matter, but I'd rather be safe here.

I forgot one minor detail.  Palmer was at SiFive when he wrote the one
patch I included, but he is now at Google.  Since it is SiFive code I can
submit it.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Mike Frysinger via Gdb-patches]

hmm, do you have push access ?  or do you need me to merge them ?
-mike

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Jim Wilson]

On Sun, Apr 18, 2021 at 8:42 PM Mike Frysinger <vapier@gentoo.org> wrote:

> hmm, do you have push access ?  or do you need me to merge them ?
>

I have write after approval access for gdb.  I'm also still listed as the
aarch64 sim maintainer, from back when I was at Linaro, which is why I
recently committed a patch for that.  But it is getting late here, so if
the patches have been approved I can commit them tomorrow.

Jim

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Andrew Burgess]

* Jim Wilson <jimw@sifive.com> [2021-04-17 10:58:07 -0700]:

> These are mostly patches extracted from riscv-gnu-toolchain with minor
> changes to apply to current FSF GDB sim.  I was careful to maintain the
> original author info, and the original commit logs when reasonable.

Maybe a silly question, but all of these authors do have an FSF
copyright assignment in place, right?  And they did all agree to pass
this code over to the FSF, right?

I don't think we can assume that just because an assignment is in
place they choose to give this code over to FSF, it would depend upon
the context in which they originally posted the code.

Thanks,
Andrew




> There are also a few extra patches from me added in, as I noticed some
> problems when reviewing the patches, and debugging issues.  Note that
> Kito and Monk were at Andes when they wrote these patches, and are now
> at SiFive.  So this is mostly Andes work, and they should get credit
> for this work.  I kept their original email addresses even though they
> won't work anymore.  We will need permission from Andes to merge the
> patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> from Palmer and myself were written at SiFive.
> 
> I tested this with a gcc make check using riscv-gnu-toolchain and pulling
> in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
> for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
> matches the old simulator port in riscv-gnu-toolchain.  I did have one
> problem with the GNUC code in mulhu function producing the wrong result,
> but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
> this is still broken with newer gcc versions I will take another look at
> that.
> 
> This code can probably use some cleanup.  I'd like to see the extensions
> in canonical arch order for instance.  But dealing with this many patches
> is unwieldy, and I wanted to retain the original authorship for the
> patches, so I'd rather do cleanup work as follow on patches.
> 
> Jim
> 
> Jim Wilson (6):
>   RISC-V sim: Fix fence.i.
>   RISC-V sim: More atomic fixes.
>   RISC-V sim: Fix ebreak, part 2.
>   RISC-V sim: Fix mingw builds.
>   RISC-V sim: Support compressed FP instructions.
>   RISC-V sim: Add zicsr support.
> 
> Kito Cheng (9):
>   RISC-V sim: Atomic fixes.
>   RISC-V sim: Fix syscall fallback.
>   RISC-V sim: Add csrr*i instructions.
>   RISC-V sim: Improve cycle and instret counts.
>   RISC-V sim: Check sbrk argument.
>   RISC-V sim: Improve branch tracing.
>   RISC-V sim: Improve tracing for slt* instructions.
>   RISC-V sim: Set brk to _end if possible.
>   RISC-V sim: Fix divw and remw.
> 
> Kuan-Lin Chen (5):
>   RISC-V sim: Fix stack pointer alignment.
>   RISC-V sim: Add link syscall support.
>   RISC-V sim: Add brk syscall.
>   RISC-V sim: Add gettimeofday.
>   RISC-V sim: Fix tracing typo.
> 
> Monk Chiang (3):
>   RISC-V: Add fp support.
>   RISC-V sim: Fix ebreak.
>   RISC-V sim: Add compressed support.
> 
> Palmer Dabbelt (1):
>   RISC-V sim: Fix for jalr.
> 
>  sim/riscv/interp.c   |   45 ++
>  sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
>  sim/riscv/sim-main.h |   16 +-
>  3 files changed, 1733 insertions(+), 118 deletions(-)
> 
> -- 
> 2.7.4
> 

Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Andrew Burgess]

* Andrew Burgess <andrew.burgess@embecosm.com> [2021-04-21 16:47:39 +0100]:

> * Jim Wilson <jimw@sifive.com> [2021-04-17 10:58:07 -0700]:
> 
> > These are mostly patches extracted from riscv-gnu-toolchain with minor
> > changes to apply to current FSF GDB sim.  I was careful to maintain the
> > original author info, and the original commit logs when reasonable.
> 
> Maybe a silly question, but all of these authors do have an FSF
> copyright assignment in place, right?  And they did all agree to pass
> this code over to the FSF, right?
> 
> I don't think we can assume that just because an assignment is in
> place they choose to give this code over to FSF, it would depend upon
> the context in which they originally posted the code.

OK, I realise you actually already addressed this point.  I don't know
how I didn't see this given it was on the very next line.

Apologies for the noise - it's been a long day :(

Thanks,
Andrew


> 
> Thanks,
> Andrew
> 
> 
> 
> 
> > There are also a few extra patches from me added in, as I noticed some
> > problems when reviewing the patches, and debugging issues.  Note that
> > Kito and Monk were at Andes when they wrote these patches, and are now
> > at SiFive.  So this is mostly Andes work, and they should get credit
> > for this work.  I kept their original email addresses even though they
> > won't work anymore.  We will need permission from Andes to merge the
> > patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> > from Palmer and myself were written at SiFive.
> > 
> > I tested this with a gcc make check using riscv-gnu-toolchain and pulling
> > in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
> > for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
> > matches the old simulator port in riscv-gnu-toolchain.  I did have one
> > problem with the GNUC code in mulhu function producing the wrong result,
> > but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
> > this is still broken with newer gcc versions I will take another look at
> > that.
> > 
> > This code can probably use some cleanup.  I'd like to see the extensions
> > in canonical arch order for instance.  But dealing with this many patches
> > is unwieldy, and I wanted to retain the original authorship for the
> > patches, so I'd rather do cleanup work as follow on patches.
> > 
> > Jim
> > 
> > Jim Wilson (6):
> >   RISC-V sim: Fix fence.i.
> >   RISC-V sim: More atomic fixes.
> >   RISC-V sim: Fix ebreak, part 2.
> >   RISC-V sim: Fix mingw builds.
> >   RISC-V sim: Support compressed FP instructions.
> >   RISC-V sim: Add zicsr support.
> > 
> > Kito Cheng (9):
> >   RISC-V sim: Atomic fixes.
> >   RISC-V sim: Fix syscall fallback.
> >   RISC-V sim: Add csrr*i instructions.
> >   RISC-V sim: Improve cycle and instret counts.
> >   RISC-V sim: Check sbrk argument.
> >   RISC-V sim: Improve branch tracing.
> >   RISC-V sim: Improve tracing for slt* instructions.
> >   RISC-V sim: Set brk to _end if possible.
> >   RISC-V sim: Fix divw and remw.
> > 
> > Kuan-Lin Chen (5):
> >   RISC-V sim: Fix stack pointer alignment.
> >   RISC-V sim: Add link syscall support.
> >   RISC-V sim: Add brk syscall.
> >   RISC-V sim: Add gettimeofday.
> >   RISC-V sim: Fix tracing typo.
> > 
> > Monk Chiang (3):
> >   RISC-V: Add fp support.
> >   RISC-V sim: Fix ebreak.
> >   RISC-V sim: Add compressed support.
> > 
> > Palmer Dabbelt (1):
> >   RISC-V sim: Fix for jalr.
> > 
> >  sim/riscv/interp.c   |   45 ++
> >  sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
> >  sim/riscv/sim-main.h |   16 +-
> >  3 files changed, 1733 insertions(+), 118 deletions(-)
> > 
> > -- 
> > 2.7.4
> >