From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id kBNNLd0he2CaOgAAWB0awg (envelope-from ) for ; Sat, 17 Apr 2021 13:58:53 -0400 Received: by simark.ca (Postfix, from userid 112) id B732E1F104; Sat, 17 Apr 2021 13:58:53 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED, MAILING_LIST_MULTI,T_DKIM_INVALID,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 89DCF1E813 for ; Sat, 17 Apr 2021 13:58:52 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A55853896819; Sat, 17 Apr 2021 17:58:51 +0000 (GMT) Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by sourceware.org (Postfix) with ESMTPS id DF83D3894C21 for ; Sat, 17 Apr 2021 17:58:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org DF83D3894C21 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jimw@sifive.com Received: by mail-pj1-x1030.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so16282858pjv.1 for ; Sat, 17 Apr 2021 10:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=QIklmHe+LYGWI1e0fxeLiZe2S1g8Mm6w59dZXil43BE=; b=FLSZrsYGZSgPkLh6bkxXqghYTHTbu+j1akbQOK1OTP2J09dVNOyug+Tn4wFY5vDJS7 bk8EN3l7W2VeJ/qJy4IlLqD0xC99CqaYuQQfjF7VkubFLtRSYbw4KKrfPBjxbStBu6sO R/+0HjK1EKDRw4XaiC9pO7NIkMQicMdkbx+EhBN/AVzg5kRmjQSzD9vjORJyT4dd1vMh S1ZAgAyiDEZ6Q+2JRFkOYsatZNXP3opx0/qbj3kZpGxv18qdS0VX5X02/P2OwIVaV8ku D0Yb+ZR51/miRk0yG8W4VmALLv4Gv7kQouSNWGPS8mgeH1J1GcpHDxCklu8QFlQHSqNk 6npw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=QIklmHe+LYGWI1e0fxeLiZe2S1g8Mm6w59dZXil43BE=; b=JjoQV4drJAHbEiIiAFgHUaSnGXVvmtY0iJaX8PlgCyOll2E6PGMrXORKrC8DNW1qtg 4LtNjEUOOMYXcJ+9H6LX5w0tXT9pePFultCZUWH7HnoxjLsMnxOmIWvYcjWhrlTCyEBW C4yAhFQnZbf4We9Ci5iX+iyRsQH+jAgfde07OMjcVvtfa0CLlhfmjPBOWR4na59C1+G+ hcaXGOE6AZgkiVGdbvD+hP3dl/DYnbLWlY2EukU2evy1v9LOq6c7ydXRF3KBCE2cxEI3 TrSQ2kyIzOJySnNFczbNpCO8/DcRguLqmFn2u+m7OWBI9Q0JptNkeM/YIQJNBVEbaEFU uZOA== X-Gm-Message-State: AOAM533CVJDuFOGAr3rLIcb+P1fOE2dHkW6Czpb7jzH0ki9gWRx0CKAV Ob7sBnxK1orMT/oE4I5zg04Zo/nFihYuLQ== X-Google-Smtp-Source: ABdhPJy2cetjX03yi/k5FRZH/zZJd+qRW+i8tm7H/38xN/EAgpPUYeqFubUxqg7Lg6OkCUvZhWReQQ== X-Received: by 2002:a17:902:6b8a:b029:ec:7fc8:7e89 with SMTP id p10-20020a1709026b8ab02900ec7fc87e89mr7458651plk.58.1618682323675; Sat, 17 Apr 2021 10:58:43 -0700 (PDT) Received: from rohan.hsd1.ca.comcast.net ([2601:646:c180:b150:1820:3ed4:975:3fbe]) by smtp.gmail.com with ESMTPSA id u4sm5030705pfk.56.2021.04.17.10.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 10:58:43 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Subject: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain. Date: Sat, 17 Apr 2021 10:58:07 -0700 Message-Id: <20210417175831.16413-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" These are mostly patches extracted from riscv-gnu-toolchain with minor changes to apply to current FSF GDB sim. I was careful to maintain the original author info, and the original commit logs when reasonable. There are also a few extra patches from me added in, as I noticed some problems when reviewing the patches, and debugging issues. Note that Kito and Monk were at Andes when they wrote these patches, and are now at SiFive. So this is mostly Andes work, and they should get credit for this work. I kept their original email addresses even though they won't work anymore. We will need permission from Andes to merge the patches into FSF GDB. Hopefully Kuan-Lin can do that for us. The patches from Palmer and myself were written at SiFive. I tested this with a gcc make check using riscv-gnu-toolchain and pulling in FSF GDB sim with my patches applied. I get 13 gcc unexpected failures for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which matches the old simulator port in riscv-gnu-toolchain. I did have one problem with the GNUC code in mulhu function producing the wrong result, but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server. If this is still broken with newer gcc versions I will take another look at that. This code can probably use some cleanup. I'd like to see the extensions in canonical arch order for instance. But dealing with this many patches is unwieldy, and I wanted to retain the original authorship for the patches, so I'd rather do cleanup work as follow on patches. Jim Jim Wilson (6): RISC-V sim: Fix fence.i. RISC-V sim: More atomic fixes. RISC-V sim: Fix ebreak, part 2. RISC-V sim: Fix mingw builds. RISC-V sim: Support compressed FP instructions. RISC-V sim: Add zicsr support. Kito Cheng (9): RISC-V sim: Atomic fixes. RISC-V sim: Fix syscall fallback. RISC-V sim: Add csrr*i instructions. RISC-V sim: Improve cycle and instret counts. RISC-V sim: Check sbrk argument. RISC-V sim: Improve branch tracing. RISC-V sim: Improve tracing for slt* instructions. RISC-V sim: Set brk to _end if possible. RISC-V sim: Fix divw and remw. Kuan-Lin Chen (5): RISC-V sim: Fix stack pointer alignment. RISC-V sim: Add link syscall support. RISC-V sim: Add brk syscall. RISC-V sim: Add gettimeofday. RISC-V sim: Fix tracing typo. Monk Chiang (3): RISC-V: Add fp support. RISC-V sim: Fix ebreak. RISC-V sim: Add compressed support. Palmer Dabbelt (1): RISC-V sim: Fix for jalr. sim/riscv/interp.c | 45 ++ sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++---- sim/riscv/sim-main.h | 16 +- 3 files changed, 1733 insertions(+), 118 deletions(-) -- 2.7.4