[PATCH] CRIS sim and it's testsuite

[PATCH] CRIS sim and it's testsuite

[Edgar E. Iglesias]

Hello,

I noticed that the condition code flags were not tested for move-like insns on CRIS. When adding code to check the flags a couple of errors in the test-cases were exposed. This patch tries to correct those.

The change introduces regressions in the tests for movu.b and movu.w, I verified with real CRISv32 hw that the test cases are OK so this seems to be an error in the simulator. I had a quick look at the cgen descriptions but saw no obvious errors, zero-extension seems do be done correctly for movu so I can't see why the N flag would get set. 

Best regards
-- 
Edgar E. Iglesias
Axis Communications AB

2007-10-01 Edgar E. Iglesias <edgar@axis.com>

	* sim/cris/asm/testutils.inc (test_move_cc): Check N and Z flags.
	* sim/cris/asm/asr.ms: Correct expected condition code flags.
	* sim/cris/asm/boundr.ms: Ditto.
	* sim/cris/asm/dstep.ms: Ditto.
	* sim/cris/asm/lsr.ms: Ditto.
	* sim/cris/asm/movecr.ms: Ditto.
	* sim/cris/asm/mover.ms: Ditto.
	* sim/cris/asm/neg.ms: Ditto.
	* sim/cris/asm/op3.ms: Check the condition code flags after the insn
	under test.
	* sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles.
	* sim/cris/asm/movecrt32.ms: Ditto.

Index: asr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/asr.ms,v
retrieving revision 1.1
diff -u -p -r1.1 asr.ms
--- asr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ asr.ms	1 Oct 2007 08:43:53 -0000
@@ -205,13 +205,13 @@
  move.d 0x5a67f19f,r3
  moveq 12,r4
  asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 5a67f1ff
 
  move.d 0x5a67f19f,r3
  moveq 4,r4
  asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 5a67f1f9
 
  move.d 0x5a67f19f,r3
Index: boundr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/boundr.ms,v
retrieving revision 1.1
diff -u -p -r1.1 boundr.ms
--- boundr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ boundr.ms	1 Oct 2007 08:43:54 -0000
@@ -24,7 +24,7 @@
  moveq -1,r4
  move.d r4,r3
  bound.d r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; ffffffff
 
  move.d 0x5432f789,r4
Index: dstep.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/dstep.ms,v
retrieving revision 1.1
diff -u -p -r1.1 dstep.ms
--- dstep.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ dstep.ms	1 Oct 2007 08:43:54 -0000
@@ -30,7 +30,7 @@
  move.d 0x5432f789,r4
  move.d 0x78134452,r3
  dstep r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 9bf3911b
 
  move.d 0xffff,r3
Index: lsr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/lsr.ms,v
retrieving revision 1.1
diff -u -p -r1.1 lsr.ms
--- lsr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ lsr.ms	1 Oct 2007 08:43:54 -0000
@@ -127,7 +127,7 @@
  moveq -1,r3
  moveq 31,r4
  lsr.w r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 0 1 0 0
  dumpr3 ; ffff0000
 
  moveq -1,r3
Index: movecr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecr.ms,v
retrieving revision 1.1
diff -u -p -r1.1 movecr.ms
--- movecr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ movecr.ms	1 Oct 2007 08:43:54 -0000
@@ -13,12 +13,12 @@
 
  moveq 0,r3
  move.b 0x94,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3
 
  moveq -1,r3
  move.w 0x4321,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
  dumpr3
 
  moveq 0,r3
Index: movecrt10.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt10.ms,v
retrieving revision 1.1
diff -u -p -r1.1 movecrt10.ms
--- movecrt10.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ movecrt10.ms	1 Oct 2007 08:43:54 -0000
@@ -1,6 +1,6 @@
 #mach: crisv10
 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 58\n
 #output: Memory source stall cycles: 0\n
 #output: Memory read-after-write stall cycles: 0\n
 #output: Movem source stall cycles: 0\n
Index: movecrt32.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt32.ms,v
retrieving revision 1.1
diff -u -p -r1.1 movecrt32.ms
--- movecrt32.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ movecrt32.ms	1 Oct 2007 08:43:54 -0000
@@ -1,6 +1,6 @@
 #mach: crisv32
 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 52\n
 #output: Memory source stall cycles: 0\n
 #output: Memory read-after-write stall cycles: 0\n
 #output: Movem source stall cycles: 0\n
Index: mover.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/mover.ms,v
retrieving revision 1.1
diff -u -p -r1.1 mover.ms
--- mover.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ mover.ms	1 Oct 2007 08:43:54 -0000
@@ -8,7 +8,7 @@
  moveq -30,r3
  moveq 5,r4
  move.b r4,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
  dumpr3
 
  move.w r4,r3
Index: neg.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/neg.ms,v
retrieving revision 1.1
diff -u -p -r1.1 neg.ms
--- neg.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ neg.ms	1 Oct 2007 08:43:54 -0000
@@ -17,7 +17,7 @@
 
  moveq 0,r3
  neg.d r3,r3
- test_move_cc 0 0 1 0
+ test_move_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x80000000,r3
@@ -49,7 +49,7 @@
 
  moveq 0,r3
  neg.w r3,r3
- test_move_cc 0 0 1 0
+ test_move_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x89ab8000,r3
@@ -81,12 +81,12 @@
 
  moveq 0,r3
  neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_move_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x89abae80,r3
  neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_move_cc 1 0 0 1
  dumpr3 ; 89abae80
 
  moveq -1,r3
Index: op3.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/op3.ms,v
retrieving revision 1.1
diff -u -p -r1.1 op3.ms
--- op3.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ op3.ms	1 Oct 2007 08:43:54 -0000
@@ -43,8 +43,8 @@ x:
 
  moveq 0,r5
  bdap 2,r10
- test_move_cc 0 0 0 0
  movu.b [r3],r5
+ test_move_cc 0 0 0 0
  dumpr3 ; aa
 
  move.d 0x42435567,r8
Index: testutils.inc
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/testutils.inc,v
retrieving revision 1.2
diff -u -p -r1.2 testutils.inc
--- testutils.inc	2 Apr 2006 11:43:44 -0000	1.2
+++ testutils.inc	1 Oct 2007 08:43:54 -0000
@@ -276,9 +276,25 @@ _start:
 	.endm
 
 	.macro test_move_cc N Z V C
-	.if ..asm.arch.cris.v32
-	clearf vc
+	.if \N
+	bpl 99f
+	nop
+	.else
+	bmi 99f
+	nop
 	.endif
+	.if \Z
+	bne 99f
+	nop
+	.else
+	beq 99f
+	nop
+	.endif
+	ba 98f
+	nop
+99:
+	fail
+98:
 	.endm
 
 ; Set the division bits

Re: [PATCH] CRIS sim and it's testsuite

[Daniel Jacobowitz]

On Wed, Oct 03, 2007 at 04:58:48PM +0200, Edgar E. Iglesias wrote:
> 2007-10-01 Edgar E. Iglesias <edgar@axis.com>
> 
> 	* sim/cris/asm/testutils.inc (test_move_cc): Check N and Z flags.
> 	* sim/cris/asm/asr.ms: Correct expected condition code flags.
> 	* sim/cris/asm/boundr.ms: Ditto.
> 	* sim/cris/asm/dstep.ms: Ditto.
> 	* sim/cris/asm/lsr.ms: Ditto.
> 	* sim/cris/asm/movecr.ms: Ditto.
> 	* sim/cris/asm/mover.ms: Ditto.
> 	* sim/cris/asm/neg.ms: Ditto.
> 	* sim/cris/asm/op3.ms: Check the condition code flags after the insn
> 	under test.
> 	* sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles.
> 	* sim/cris/asm/movecrt32.ms: Ditto.

H-P, are you going to respond to this?  I certainly can't make any
educated comments about it.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [PATCH] CRIS sim and it's testsuite

[Hans-Peter Nilsson]

> Date: Thu, 11 Oct 2007 14:06:12 -0400
> From: Daniel Jacobowitz <drow@false.org>

> On Wed, Oct 03, 2007 at 04:58:48PM +0200, Edgar E. Iglesias wrote:
> > 2007-10-01 Edgar E. Iglesias <edgar@axis.com>
> > 
> > 	* sim/cris/asm/testutils.inc (test_move_cc): Check N and Z flags.
(etc)
> H-P, are you going to respond to this?  I certainly can't make any
> educated comments about it.

Yes I am, sorry for the delay.

brgds, H-P

Re: [PATCH] CRIS sim and it's testsuite

[Hans-Peter Nilsson]

(Binutils CC:ed, because it's the official home, which might
otherwise seem odd for a simulator-only CGEN port.)

> Date: Wed, 3 Oct 2007 16:58:48 +0200
> From: "Edgar E. Iglesias" <edgar@axis.com>

> The change introduces regressions in the tests for movu.b and
> movu.w, I verified with real CRISv32 hw that the test cases
> are OK so this seems to be an error in the simulator.

Indeed.  Thanks for the analysis and sorry about the delay.

> I had a
> quick look at the cgen descriptions but saw no obvious errors,
> zero-extension seems do be done correctly for movu so I can't
> see why the N flag would get set.

Yeah, I had to stare at it a few minutes too.  It's not obvious
until you see it. :-]  A copy of the original operand isn't much
good for "testing" the zero-extended N flag even if you call it
"newval".

I adjusted movs too for consistency.  Note that the other
movs/movu insns (with non-register source) already do the right
thing.

I regtested with the gcc testsuite for a month-old tree I had
convenient.  Next: the testsuite patches.

src/cpu:
	* cris.cpu (movs, movu): Use result of extension operation when
        updating flags.

Most or all generated files changed because of some formatting
change (not the GPLv3 one) in the template, though the only
operational change is in cris/semcrisv{10,32}f-switch.c.

src/sim:
        * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c,
        cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c,
        cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c,
        cris/decodev10.h, cris/decodev32.c, cris/decodev32.h,
        cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c,
        cris/semcrisv32f-switch.c: Regenerate.

[Diff for generated files elided.]

Index: cris.cpu
===================================================================
RCS file: /cvs/src/src/cpu/cris.cpu,v
retrieving revision 1.6
diff -p -u -r1.6 cris.cpu
--- cris.cpu	5 Jul 2007 09:49:03 -0000	1.6
+++ cris.cpu	22 Oct 2007 15:51:25 -0000
@@ -2033,9 +2033,10 @@
  (.pmacro
   (BW)
   (sequence
-    ((BW newval))
-    (set newval Rs)
-    (set Rd (ext SI newval))
+    ((BW tmpops) (SI newval))
+    (set tmpops Rs)
+    (set newval (ext SI tmpops))
+    (set Rd newval)
     (setf-move SI newval)))
 )
 
@@ -2060,9 +2061,10 @@
  (.pmacro
   (BW)
   (sequence
-    ((BW newval))
-    (set newval Rs)
-    (set Rd (zext SI newval))
+    ((BW tmpops) (SI newval))
+    (set tmpops Rs)
+    (set newval (zext SI tmpops))
+    (set Rd newval)
     (setf-move SI newval)))
 )
 

brgds, H-P

Re: [PATCH] CRIS sim and it's testsuite

[Hans-Peter Nilsson]

> Date: Wed, 3 Oct 2007 16:58:48 +0200
> From: "Edgar E. Iglesias" <edgar@axis.com>

> I noticed that the condition code flags were not tested for
> move-like insns on CRIS.

Thanks for looking into this.  Yes, the test_move_cc macro was
totally fudged.  I can only guess I stubbed it and meant to
revisit that part but just forgot.

Your change adds code to just test N and Z though the intention
of test_move_cc is to also test C and V, for pre-v32.  When
fixing that, I had to adjust the jsr testcase as seen.  I also
noticed that there were more flaws in the neg test; the V and C
flags should always be tested as it's an arithmetic insn and the
formerly unused/untested values for V and C were wrong.  Noting
the lack of non-arithmetic V and C tests for v32, I added a new
test-case to check that V and C aren't affected for v32, for
some common insns and values.  I'm not claiming full coverage
there, just better than not testing V and C for v32 at all for
those insns.

> When adding code to check the flags a
> couple of errors in the test-cases were exposed. This patch
> tries to correct those.

Thanks.  I merged my additional adjustments and checked in the
following.

sim/testsuite:

2007-10-22  Edgar E. Iglesias <edgar@axis.com>
	    Hans-Peter Nilsson  <hp@axis.com>

	* sim/cris/asm/testutils.inc (test_move_cc): Add missing call to
	test_cc.
	* sim/cris/asm/asr.ms: Correct expected condition code flags.
	* sim/cris/asm/boundr.ms: Ditto.
	* sim/cris/asm/dstep.ms: Ditto.
	* sim/cris/asm/lsr.ms: Ditto.
	* sim/cris/asm/movecr.ms: Ditto.
	* sim/cris/asm/mover.ms: Ditto.
	* sim/cris/asm/neg.ms: Ditto.  Use test_cc, not test_move_cc.
	* sim/cris/asm/op3.ms: Check the condition code flags after the insn
	under test.
	* sim/cris/asm/movecrt10.ms: Update expected number of simulated
	cycles.
	* sim/cris/asm/movecrt32.ms: Ditto.
	* sim/cris/asm/jsr.ms: Don't use local label 8.
	* sim/cris/asm/nonvcv32.ms: New test.

Index: sim/cris/asm/testutils.inc
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/testutils.inc,v
retrieving revision 1.2
diff -p -u -r1.2 testutils.inc
--- sim/cris/asm/testutils.inc	2 Apr 2006 11:43:44 -0000	1.2
+++ sim/cris/asm/testutils.inc	22 Oct 2007 16:39:40 -0000
@@ -277,7 +277,13 @@ _start:
 
 	.macro test_move_cc N Z V C
 	.if ..asm.arch.cris.v32
+	; V and C aren't affected on v32, so to re-use the test-cases,
+	; we fake them cleared.  There's a separate test, nonvcv32.ms
+	; covering this omission.
 	clearf vc
+	test_cc \N \Z 0 0
+	.else
+	test_cc \N \Z \V \C
 	.endif
 	.endm
 
Index: sim/cris/asm/asr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/asr.ms,v
retrieving revision 1.1
diff -p -u -r1.1 asr.ms
--- sim/cris/asm/asr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/asr.ms	22 Oct 2007 16:39:39 -0000
@@ -205,13 +205,13 @@
  move.d 0x5a67f19f,r3
  moveq 12,r4
  asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 5a67f1ff
 
  move.d 0x5a67f19f,r3
  moveq 4,r4
  asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 5a67f1f9
 
  move.d 0x5a67f19f,r3
Index: sim/cris/asm/boundr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/boundr.ms,v
retrieving revision 1.1
diff -p -u -r1.1 boundr.ms
--- sim/cris/asm/boundr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/boundr.ms	22 Oct 2007 16:39:39 -0000
@@ -24,7 +24,7 @@
  moveq -1,r4
  move.d r4,r3
  bound.d r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; ffffffff
 
  move.d 0x5432f789,r4
Index: sim/cris/asm/dstep.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/dstep.ms,v
retrieving revision 1.1
diff -p -u -r1.1 dstep.ms
--- sim/cris/asm/dstep.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/dstep.ms	22 Oct 2007 16:39:39 -0000
@@ -30,7 +30,7 @@
  move.d 0x5432f789,r4
  move.d 0x78134452,r3
  dstep r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3 ; 9bf3911b
 
  move.d 0xffff,r3
Index: sim/cris/asm/jsr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/jsr.ms,v
retrieving revision 1.1
diff -p -u -r1.1 jsr.ms
--- sim/cris/asm/jsr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/jsr.ms	22 Oct 2007 16:39:39 -0000
@@ -41,7 +41,8 @@ x:
  nop
  quit
 
-8:
+; Can't use local label 8 or 9, as they're used by test_move_cc.
+y:
  move srp,r3
  sub.d 7b,r3
  dumpr3
@@ -78,7 +79,7 @@ x:
  move srp,r3
  sub.d 7b,r3
  dumpr3
- jump 8b
+ jump y
  .if ..asm.arch.cris.v32
  nop
  .endif
Index: sim/cris/asm/lsr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/lsr.ms,v
retrieving revision 1.1
diff -p -u -r1.1 lsr.ms
--- sim/cris/asm/lsr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/lsr.ms	22 Oct 2007 16:39:39 -0000
@@ -127,7 +127,7 @@
  moveq -1,r3
  moveq 31,r4
  lsr.w r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 0 1 0 0
  dumpr3 ; ffff0000
 
  moveq -1,r3
Index: sim/cris/asm/movecr.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecr.ms,v
retrieving revision 1.1
diff -p -u -r1.1 movecr.ms
--- sim/cris/asm/movecr.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/movecr.ms	22 Oct 2007 16:39:39 -0000
@@ -13,12 +13,12 @@
 
  moveq 0,r3
  move.b 0x94,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
  dumpr3
 
  moveq -1,r3
  move.w 0x4321,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
  dumpr3
 
  moveq 0,r3
Index: sim/cris/asm/movecrt10.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt10.ms,v
retrieving revision 1.1
diff -p -u -r1.1 movecrt10.ms
--- sim/cris/asm/movecrt10.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/movecrt10.ms	22 Oct 2007 16:39:39 -0000
@@ -1,6 +1,6 @@
 #mach: crisv10
 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 82\n
 #output: Memory source stall cycles: 0\n
 #output: Memory read-after-write stall cycles: 0\n
 #output: Movem source stall cycles: 0\n
Index: sim/cris/asm/movecrt32.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt32.ms,v
retrieving revision 1.1
diff -p -u -r1.1 movecrt32.ms
--- sim/cris/asm/movecrt32.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/movecrt32.ms	22 Oct 2007 16:39:39 -0000
@@ -1,6 +1,6 @@
 #mach: crisv32
 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 82\n
 #output: Memory source stall cycles: 0\n
 #output: Memory read-after-write stall cycles: 0\n
 #output: Movem source stall cycles: 0\n
Index: sim/cris/asm/mover.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/mover.ms,v
retrieving revision 1.1
diff -p -u -r1.1 mover.ms
--- sim/cris/asm/mover.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/mover.ms	22 Oct 2007 16:39:39 -0000
@@ -8,7 +8,7 @@
  moveq -30,r3
  moveq 5,r4
  move.b r4,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
  dumpr3
 
  move.w r4,r3
Index: sim/cris/asm/neg.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/neg.ms,v
retrieving revision 1.1
diff -p -u -r1.1 neg.ms
--- sim/cris/asm/neg.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/neg.ms	22 Oct 2007 16:39:39 -0000
@@ -6,97 +6,97 @@
  moveq 0,r3
  moveq 1,r4
  neg.d r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ffffffff
 
  moveq 1,r3
  moveq 0,r4
  neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ffffffff
 
  moveq 0,r3
  neg.d r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x80000000,r3
  neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 1 1
  dumpr3 ; 80000000
 
  moveq -1,r3
  neg.d r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
  dumpr3 ; 1
 
  move.d 0x456789ab,r3
  neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ba987655
 
  moveq 0,r3
  moveq 1,r4
  neg.w r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ffff
 
  moveq 1,r3
  moveq 0,r4
  neg.w r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ffff
 
  moveq 0,r3
  neg.w r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x89ab8000,r3
  neg.w r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 1 1
  dumpr3 ; 89ab8000
 
  moveq -1,r3
  neg.w r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
  dumpr3 ; ffff0001
 
  move.d 0x456789ab,r3
  neg.w r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
  dumpr3 ; 45677655
 
  moveq 0,r3
  moveq 1,r4
  neg.b r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ff
 
  moveq 1,r3
  moveq 0,r4
  neg.b r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
  dumpr3 ; ff
 
  moveq 0,r3
  neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
  dumpr3 ; 0
 
  move.d 0x89abae80,r3
  neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_cc 1 0 1 1
  dumpr3 ; 89abae80
 
  moveq -1,r3
  neg.b r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
  dumpr3 ; ffffff01
 
  move.d 0x456789ab,r3
  neg.b r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
  dumpr3 ; 45678955
 
  quit
Index: sim/cris/asm/nonvcv32.ms
===================================================================
RCS file: sim/cris/asm/nonvcv32.ms
diff -N sim/cris/asm/nonvcv32.ms
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ sim/cris/asm/nonvcv32.ms	22 Oct 2007 16:39:39 -0000
@@ -0,0 +1,167 @@
+# mach: crisv32
+
+ .include "testutils.inc"
+
+; Check for various non-arithmetic insns that C and V are not affected
+; on v32 (where they were on v10), as the generic tests don't cover
+; that; they are cleared before testing.
+
+; First, a macro testing that VC are unaffected, not counting previous
+; register contents.
+ .macro nonvc0 insn op
+ move.d $r0,$r3
+ setf vc
+ .ifnc \insn,swapnwbr
+ \insn \op,$r3
+ .else
+ \insn $r3
+ .endif
+ bcc 9f
+ nop
+ bvc 9f
+ nop
+ move.d $r0,$r3
+ clearf vc
+ .ifnc \insn,swapnwbr
+ \insn \op,$r3
+ .else
+ \insn $r3
+ .endif
+ bcs 9f
+ nop
+ bvc 8f
+ nop
+9:
+ fail
+8:
+ .endm
+
+; Use the above, but initialize the non-parameter operand to a value.
+ .macro nonvc1 insn val op
+ move.d \val,$r0
+ nonvc0 \insn,\op
+ .endm
+
+; Use the above, iterating over various values.
+ .macro nonvc2 insn op
+ .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
+ nonvc1 \insn,\p,\op
+ nonvc1 \insn,-\p,\op
+ .endr
+ .endm
+
+ .macro nonvc2q insn op min=-63 max=63
+ .if \op >= \min &&&& \op <= \max
+ nonvc2 \insn,\op
+ .endif
+ .endm
+
+; The above, for each .b .w .d insn variant.
+ .macro nonvcbwd insn op
+ .irp s,.b,.w,.d
+ nonvc2 \insn\s,\op
+ .endr
+ .endm
+
+; For various insns with register, dword constant and memory operands.
+ .macro nonvcitermcd op=[$r4]
+ nonvc2 and.d,\op
+ nonvc2 move.d,\op
+ nonvc2 or.d,\op
+ .endm
+
+; Similar, for various insns with register, word constant and memory operands.
+ .macro nonvcitermcw op=[$r4]
+ nonvcitermcd \op
+ nonvc2 and.w,\op
+ nonvc2 move.w,\op
+ nonvc2 or.w,\op
+ nonvc2 movs.w,\op
+ nonvc2 movu.w,\op
+ .endm
+
+; Similar, for various insns with register, byte constant and memory operands.
+ .macro nonvcitermcb op=[$r4]
+ nonvcitermcw \op
+ nonvc2 and.b,\op
+ nonvc2 move.b,\op
+ nonvc2 or.b,\op
+ nonvc2 movs.b,\op
+ nonvc2 movu.b,\op
+ .endm
+
+; Similar, for insns with quick constant operands.
+ .macro nonvciterq op
+ nonvcitermcb \op
+ nonvc2 bound.b,\op
+ nonvc2q andq,\op,min=-32,max=31
+ nonvc2q asrq,\op,min=0,max=31
+ nonvc2q lsrq,\op,min=0,max=31
+ nonvc2q orq,\op,min=-32,max=31
+ nonvc2q moveq,\op,min=-32,max=31
+ .endm
+
+; Similar, for insns with register operands.
+ .macro nonvciterr op
+ nonvcitermcb \op
+ nonvcbwd bound,\op
+ nonvc2 abs,\op
+ nonvcbwd asr,\op
+ nonvc2 dstep,\op
+ nonvcbwd lsr,\op
+ nonvcbwd lsl,\op
+ nonvc2 lz,\op
+ nonvc2 swapnwbr
+ nonvc2 xor,\op
+ .endm
+
+; Test all applicable constant, register and memory variants of a value.
+ .macro tst op
+; Constants
+ .if (\op <= 31 &&&& \op >= -32)
+ nonvciterq \op
+ .elseif (\op <= 255 &&&& \op >= -128)
+ nonvcitermcb \op
+ nonvcbwd bound,\op
+ .elseif (\op <= 65535 &&&& \op >= -32767)
+ nonvcitermcw \op
+ nonvc2 bound.w,\op
+ nonvc2 bound.d,\op
+ .else
+ nonvcitermcd \op
+ nonvc2 bound.d,\op
+ .endif
+; Registers
+ move.d \op,$r4
+ nonvciterr $r4
+; Memory
+ nonvcitermcb [$r5]
+ addq 4,$r5
+ .section .rodata
+ .dword \op
+ .previous
+ .endm
+
+; As above but negation too.
+ .macro tstpm op
+ tst \op
+ tst -\op
+ .endm
+
+
+; Set up for the actual test.
+
+ start
+ move.d c0,$r5
+
+ .section .rodata
+c0:
+ .previous
+
+; Finally, test.
+
+ .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
+ tstpm \x
+ .endr 
+
+ pass
Index: sim/cris/asm/op3.ms
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/op3.ms,v
retrieving revision 1.1
diff -p -u -r1.1 op3.ms
--- sim/cris/asm/op3.ms	21 Nov 2005 04:48:19 -0000	1.1
+++ sim/cris/asm/op3.ms	22 Oct 2007 16:39:39 -0000
@@ -43,8 +43,8 @@ x:
 
  moveq 0,r5
  bdap 2,r10
- test_move_cc 0 0 0 0
  movu.b [r3],r5
+ test_move_cc 0 0 0 0
  dumpr3 ; aa
 
  move.d 0x42435567,r8

brgds, H-P

Re: [PATCH] CRIS sim and it's testsuite

[Edgar E. Iglesias]

On Mon, Oct 22, 2007 at 06:53:39PM +0200, Hans-Peter Nilsson wrote:
> > Date: Wed, 3 Oct 2007 16:58:48 +0200
> > From: "Edgar E. Iglesias" <edgar@axis.com>
> 
> > I noticed that the condition code flags were not tested for
> > move-like insns on CRIS.
> 
> Thanks for looking into this.  Yes, the test_move_cc macro was
> totally fudged.  I can only guess I stubbed it and meant to
> revisit that part but just forgot.
> 
> Your change adds code to just test N and Z though the intention
> of test_move_cc is to also test C and V, for pre-v32.  When
> fixing that, I had to adjust the jsr testcase as seen.  I also
> noticed that there were more flaws in the neg test; the V and C
> flags should always be tested as it's an arithmetic insn and the
> formerly unused/untested values for V and C were wrong.  Noting
> the lack of non-arithmetic V and C tests for v32, I added a new
> test-case to check that V and C aren't affected for v32, for
> some common insns and values.  I'm not claiming full coverage
> there, just better than not testing V and C for v32 at all for
> those insns.

Thanks for taking care of all this H-P.

Best regards
-- 
Edgar E. Iglesias
Axis Communications AB