From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13429 invoked by alias); 3 Oct 2007 14:58:57 -0000 Received: (qmail 13420 invoked by uid 22791); 3 Oct 2007 14:58:56 -0000 X-Spam-Check-By: sourceware.org Received: from miranda.se.axis.com (HELO miranda.se.axis.com) (193.13.178.8) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 03 Oct 2007 14:58:52 +0000 Received: from axis.com (edgar.se.axis.com [10.92.151.1]) by miranda.se.axis.com (8.13.4/8.13.4/Debian-3sarge3) with ESMTP id l93Ewm9o007182 for ; Wed, 3 Oct 2007 16:58:48 +0200 Received: (qmail 13199 invoked by uid 400); 3 Oct 2007 14:58:48 -0000 Date: Wed, 03 Oct 2007 14:58:00 -0000 From: "Edgar E. Iglesias" To: gdb-patches@sourceware.org Cc: hans-peter.nilsson@axis.com Subject: [PATCH] CRIS sim and it's testsuite Message-ID: <20071003145848.GG16132@edgar.underground.se.axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00030.txt.bz2 Hello, I noticed that the condition code flags were not tested for move-like insns on CRIS. When adding code to check the flags a couple of errors in the test-cases were exposed. This patch tries to correct those. The change introduces regressions in the tests for movu.b and movu.w, I verified with real CRISv32 hw that the test cases are OK so this seems to be an error in the simulator. I had a quick look at the cgen descriptions but saw no obvious errors, zero-extension seems do be done correctly for movu so I can't see why the N flag would get set. Best regards -- Edgar E. Iglesias Axis Communications AB 2007-10-01 Edgar E. Iglesias * sim/cris/asm/testutils.inc (test_move_cc): Check N and Z flags. * sim/cris/asm/asr.ms: Correct expected condition code flags. * sim/cris/asm/boundr.ms: Ditto. * sim/cris/asm/dstep.ms: Ditto. * sim/cris/asm/lsr.ms: Ditto. * sim/cris/asm/movecr.ms: Ditto. * sim/cris/asm/mover.ms: Ditto. * sim/cris/asm/neg.ms: Ditto. * sim/cris/asm/op3.ms: Check the condition code flags after the insn under test. * sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles. * sim/cris/asm/movecrt32.ms: Ditto. Index: asr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/asr.ms,v retrieving revision 1.1 diff -u -p -r1.1 asr.ms --- asr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ asr.ms 1 Oct 2007 08:43:53 -0000 @@ -205,13 +205,13 @@ move.d 0x5a67f19f,r3 moveq 12,r4 asr.b r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 5a67f1ff move.d 0x5a67f19f,r3 moveq 4,r4 asr.b r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 5a67f1f9 move.d 0x5a67f19f,r3 Index: boundr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/boundr.ms,v retrieving revision 1.1 diff -u -p -r1.1 boundr.ms --- boundr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ boundr.ms 1 Oct 2007 08:43:54 -0000 @@ -24,7 +24,7 @@ moveq -1,r4 move.d r4,r3 bound.d r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; ffffffff move.d 0x5432f789,r4 Index: dstep.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/dstep.ms,v retrieving revision 1.1 diff -u -p -r1.1 dstep.ms --- dstep.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ dstep.ms 1 Oct 2007 08:43:54 -0000 @@ -30,7 +30,7 @@ move.d 0x5432f789,r4 move.d 0x78134452,r3 dstep r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 9bf3911b move.d 0xffff,r3 Index: lsr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/lsr.ms,v retrieving revision 1.1 diff -u -p -r1.1 lsr.ms --- lsr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ lsr.ms 1 Oct 2007 08:43:54 -0000 @@ -127,7 +127,7 @@ moveq -1,r3 moveq 31,r4 lsr.w r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 0 1 0 0 dumpr3 ; ffff0000 moveq -1,r3 Index: movecr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecr.ms,v retrieving revision 1.1 diff -u -p -r1.1 movecr.ms --- movecr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ movecr.ms 1 Oct 2007 08:43:54 -0000 @@ -13,12 +13,12 @@ moveq 0,r3 move.b 0x94,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 moveq -1,r3 move.w 0x4321,r3 - test_move_cc 1 0 0 0 + test_move_cc 0 0 0 0 dumpr3 moveq 0,r3 Index: movecrt10.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt10.ms,v retrieving revision 1.1 diff -u -p -r1.1 movecrt10.ms --- movecrt10.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ movecrt10.ms 1 Oct 2007 08:43:54 -0000 @@ -1,6 +1,6 @@ #mach: crisv10 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 22\n +#output: Basic clock cycles, total @: 58\n #output: Memory source stall cycles: 0\n #output: Memory read-after-write stall cycles: 0\n #output: Movem source stall cycles: 0\n Index: movecrt32.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt32.ms,v retrieving revision 1.1 diff -u -p -r1.1 movecrt32.ms --- movecrt32.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ movecrt32.ms 1 Oct 2007 08:43:54 -0000 @@ -1,6 +1,6 @@ #mach: crisv32 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 22\n +#output: Basic clock cycles, total @: 52\n #output: Memory source stall cycles: 0\n #output: Memory read-after-write stall cycles: 0\n #output: Movem source stall cycles: 0\n Index: mover.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/mover.ms,v retrieving revision 1.1 diff -u -p -r1.1 mover.ms --- mover.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ mover.ms 1 Oct 2007 08:43:54 -0000 @@ -8,7 +8,7 @@ moveq -30,r3 moveq 5,r4 move.b r4,r3 - test_move_cc 1 0 0 0 + test_move_cc 0 0 0 0 dumpr3 move.w r4,r3 Index: neg.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/neg.ms,v retrieving revision 1.1 diff -u -p -r1.1 neg.ms --- neg.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ neg.ms 1 Oct 2007 08:43:54 -0000 @@ -17,7 +17,7 @@ moveq 0,r3 neg.d r3,r3 - test_move_cc 0 0 1 0 + test_move_cc 0 1 0 0 dumpr3 ; 0 move.d 0x80000000,r3 @@ -49,7 +49,7 @@ moveq 0,r3 neg.w r3,r3 - test_move_cc 0 0 1 0 + test_move_cc 0 1 0 0 dumpr3 ; 0 move.d 0x89ab8000,r3 @@ -81,12 +81,12 @@ moveq 0,r3 neg.b r3,r3 - test_move_cc 0 0 1 0 + test_move_cc 0 1 0 0 dumpr3 ; 0 move.d 0x89abae80,r3 neg.b r3,r3 - test_move_cc 0 0 1 0 + test_move_cc 1 0 0 1 dumpr3 ; 89abae80 moveq -1,r3 Index: op3.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/op3.ms,v retrieving revision 1.1 diff -u -p -r1.1 op3.ms --- op3.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ op3.ms 1 Oct 2007 08:43:54 -0000 @@ -43,8 +43,8 @@ x: moveq 0,r5 bdap 2,r10 - test_move_cc 0 0 0 0 movu.b [r3],r5 + test_move_cc 0 0 0 0 dumpr3 ; aa move.d 0x42435567,r8 Index: testutils.inc =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/testutils.inc,v retrieving revision 1.2 diff -u -p -r1.2 testutils.inc --- testutils.inc 2 Apr 2006 11:43:44 -0000 1.2 +++ testutils.inc 1 Oct 2007 08:43:54 -0000 @@ -276,9 +276,25 @@ _start: .endm .macro test_move_cc N Z V C - .if ..asm.arch.cris.v32 - clearf vc + .if \N + bpl 99f + nop + .else + bmi 99f + nop .endif + .if \Z + bne 99f + nop + .else + beq 99f + nop + .endif + ba 98f + nop +99: + fail +98: .endm ; Set the division bits