From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17033 invoked by alias); 22 Oct 2007 16:53:54 -0000 Received: (qmail 17019 invoked by uid 22791); 22 Oct 2007 16:53:51 -0000 X-Spam-Check-By: sourceware.org Received: from nic2.axis.se (HELO krynn.se.axis.com) (193.13.178.10) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 22 Oct 2007 16:53:44 +0000 Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.83.5.18]) by krynn.se.axis.com (8.13.4/8.13.4/Debian-3sarge3) with ESMTP id l9MGreDO030140; Mon, 22 Oct 2007 18:53:40 +0200 Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id l9MGrdbH021462; Mon, 22 Oct 2007 18:53:39 +0200 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id l9MGrdTQ021458; Mon, 22 Oct 2007 18:53:39 +0200 Date: Mon, 22 Oct 2007 16:56:00 -0000 Message-Id: <200710221653.l9MGrdTQ021458@ignucius.se.axis.com> From: Hans-Peter Nilsson To: edgar.iglesias@axis.com CC: gdb-patches@sourceware.org, hans-peter.nilsson@axis.com In-reply-to: <20071003145848.GG16132@edgar.underground.se.axis.com> Subject: Re: [PATCH] CRIS sim and it's testsuite Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00510.txt.bz2 > Date: Wed, 3 Oct 2007 16:58:48 +0200 > From: "Edgar E. Iglesias" > I noticed that the condition code flags were not tested for > move-like insns on CRIS. Thanks for looking into this. Yes, the test_move_cc macro was totally fudged. I can only guess I stubbed it and meant to revisit that part but just forgot. Your change adds code to just test N and Z though the intention of test_move_cc is to also test C and V, for pre-v32. When fixing that, I had to adjust the jsr testcase as seen. I also noticed that there were more flaws in the neg test; the V and C flags should always be tested as it's an arithmetic insn and the formerly unused/untested values for V and C were wrong. Noting the lack of non-arithmetic V and C tests for v32, I added a new test-case to check that V and C aren't affected for v32, for some common insns and values. I'm not claiming full coverage there, just better than not testing V and C for v32 at all for those insns. > When adding code to check the flags a > couple of errors in the test-cases were exposed. This patch > tries to correct those. Thanks. I merged my additional adjustments and checked in the following. sim/testsuite: 2007-10-22 Edgar E. Iglesias Hans-Peter Nilsson * sim/cris/asm/testutils.inc (test_move_cc): Add missing call to test_cc. * sim/cris/asm/asr.ms: Correct expected condition code flags. * sim/cris/asm/boundr.ms: Ditto. * sim/cris/asm/dstep.ms: Ditto. * sim/cris/asm/lsr.ms: Ditto. * sim/cris/asm/movecr.ms: Ditto. * sim/cris/asm/mover.ms: Ditto. * sim/cris/asm/neg.ms: Ditto. Use test_cc, not test_move_cc. * sim/cris/asm/op3.ms: Check the condition code flags after the insn under test. * sim/cris/asm/movecrt10.ms: Update expected number of simulated cycles. * sim/cris/asm/movecrt32.ms: Ditto. * sim/cris/asm/jsr.ms: Don't use local label 8. * sim/cris/asm/nonvcv32.ms: New test. Index: sim/cris/asm/testutils.inc =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/testutils.inc,v retrieving revision 1.2 diff -p -u -r1.2 testutils.inc --- sim/cris/asm/testutils.inc 2 Apr 2006 11:43:44 -0000 1.2 +++ sim/cris/asm/testutils.inc 22 Oct 2007 16:39:40 -0000 @@ -277,7 +277,13 @@ _start: .macro test_move_cc N Z V C .if ..asm.arch.cris.v32 + ; V and C aren't affected on v32, so to re-use the test-cases, + ; we fake them cleared. There's a separate test, nonvcv32.ms + ; covering this omission. clearf vc + test_cc \N \Z 0 0 + .else + test_cc \N \Z \V \C .endif .endm Index: sim/cris/asm/asr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/asr.ms,v retrieving revision 1.1 diff -p -u -r1.1 asr.ms --- sim/cris/asm/asr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/asr.ms 22 Oct 2007 16:39:39 -0000 @@ -205,13 +205,13 @@ move.d 0x5a67f19f,r3 moveq 12,r4 asr.b r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 5a67f1ff move.d 0x5a67f19f,r3 moveq 4,r4 asr.b r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 5a67f1f9 move.d 0x5a67f19f,r3 Index: sim/cris/asm/boundr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/boundr.ms,v retrieving revision 1.1 diff -p -u -r1.1 boundr.ms --- sim/cris/asm/boundr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/boundr.ms 22 Oct 2007 16:39:39 -0000 @@ -24,7 +24,7 @@ moveq -1,r4 move.d r4,r3 bound.d r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; ffffffff move.d 0x5432f789,r4 Index: sim/cris/asm/dstep.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/dstep.ms,v retrieving revision 1.1 diff -p -u -r1.1 dstep.ms --- sim/cris/asm/dstep.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/dstep.ms 22 Oct 2007 16:39:39 -0000 @@ -30,7 +30,7 @@ move.d 0x5432f789,r4 move.d 0x78134452,r3 dstep r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 ; 9bf3911b move.d 0xffff,r3 Index: sim/cris/asm/jsr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/jsr.ms,v retrieving revision 1.1 diff -p -u -r1.1 jsr.ms --- sim/cris/asm/jsr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/jsr.ms 22 Oct 2007 16:39:39 -0000 @@ -41,7 +41,8 @@ x: nop quit -8: +; Can't use local label 8 or 9, as they're used by test_move_cc. +y: move srp,r3 sub.d 7b,r3 dumpr3 @@ -78,7 +79,7 @@ x: move srp,r3 sub.d 7b,r3 dumpr3 - jump 8b + jump y .if ..asm.arch.cris.v32 nop .endif Index: sim/cris/asm/lsr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/lsr.ms,v retrieving revision 1.1 diff -p -u -r1.1 lsr.ms --- sim/cris/asm/lsr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/lsr.ms 22 Oct 2007 16:39:39 -0000 @@ -127,7 +127,7 @@ moveq -1,r3 moveq 31,r4 lsr.w r4,r3 - test_move_cc 0 0 0 0 + test_move_cc 0 1 0 0 dumpr3 ; ffff0000 moveq -1,r3 Index: sim/cris/asm/movecr.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecr.ms,v retrieving revision 1.1 diff -p -u -r1.1 movecr.ms --- sim/cris/asm/movecr.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/movecr.ms 22 Oct 2007 16:39:39 -0000 @@ -13,12 +13,12 @@ moveq 0,r3 move.b 0x94,r3 - test_move_cc 0 0 0 0 + test_move_cc 1 0 0 0 dumpr3 moveq -1,r3 move.w 0x4321,r3 - test_move_cc 1 0 0 0 + test_move_cc 0 0 0 0 dumpr3 moveq 0,r3 Index: sim/cris/asm/movecrt10.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt10.ms,v retrieving revision 1.1 diff -p -u -r1.1 movecrt10.ms --- sim/cris/asm/movecrt10.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/movecrt10.ms 22 Oct 2007 16:39:39 -0000 @@ -1,6 +1,6 @@ #mach: crisv10 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 22\n +#output: Basic clock cycles, total @: 82\n #output: Memory source stall cycles: 0\n #output: Memory read-after-write stall cycles: 0\n #output: Movem source stall cycles: 0\n Index: sim/cris/asm/movecrt32.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movecrt32.ms,v retrieving revision 1.1 diff -p -u -r1.1 movecrt32.ms --- sim/cris/asm/movecrt32.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/movecrt32.ms 22 Oct 2007 16:39:39 -0000 @@ -1,6 +1,6 @@ #mach: crisv32 #output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n -#output: Basic clock cycles, total @: 22\n +#output: Basic clock cycles, total @: 82\n #output: Memory source stall cycles: 0\n #output: Memory read-after-write stall cycles: 0\n #output: Movem source stall cycles: 0\n Index: sim/cris/asm/mover.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/mover.ms,v retrieving revision 1.1 diff -p -u -r1.1 mover.ms --- sim/cris/asm/mover.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/mover.ms 22 Oct 2007 16:39:39 -0000 @@ -8,7 +8,7 @@ moveq -30,r3 moveq 5,r4 move.b r4,r3 - test_move_cc 1 0 0 0 + test_move_cc 0 0 0 0 dumpr3 move.w r4,r3 Index: sim/cris/asm/neg.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/neg.ms,v retrieving revision 1.1 diff -p -u -r1.1 neg.ms --- sim/cris/asm/neg.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/neg.ms 22 Oct 2007 16:39:39 -0000 @@ -6,97 +6,97 @@ moveq 0,r3 moveq 1,r4 neg.d r4,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ffffffff moveq 1,r3 moveq 0,r4 neg.d r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ffffffff moveq 0,r3 neg.d r3,r3 - test_move_cc 0 0 1 0 + test_cc 0 1 0 0 dumpr3 ; 0 move.d 0x80000000,r3 neg.d r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 1 1 dumpr3 ; 80000000 moveq -1,r3 neg.d r3,r3 - test_move_cc 0 0 0 0 + test_cc 0 0 0 1 dumpr3 ; 1 move.d 0x456789ab,r3 neg.d r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ba987655 moveq 0,r3 moveq 1,r4 neg.w r4,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ffff moveq 1,r3 moveq 0,r4 neg.w r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ffff moveq 0,r3 neg.w r3,r3 - test_move_cc 0 0 1 0 + test_cc 0 1 0 0 dumpr3 ; 0 move.d 0x89ab8000,r3 neg.w r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 1 1 dumpr3 ; 89ab8000 moveq -1,r3 neg.w r3,r3 - test_move_cc 0 0 0 0 + test_cc 0 0 0 1 dumpr3 ; ffff0001 move.d 0x456789ab,r3 neg.w r3,r3 - test_move_cc 0 0 0 0 + test_cc 0 0 0 1 dumpr3 ; 45677655 moveq 0,r3 moveq 1,r4 neg.b r4,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ff moveq 1,r3 moveq 0,r4 neg.b r3,r3 - test_move_cc 1 0 0 0 + test_cc 1 0 0 1 dumpr3 ; ff moveq 0,r3 neg.b r3,r3 - test_move_cc 0 0 1 0 + test_cc 0 1 0 0 dumpr3 ; 0 move.d 0x89abae80,r3 neg.b r3,r3 - test_move_cc 0 0 1 0 + test_cc 1 0 1 1 dumpr3 ; 89abae80 moveq -1,r3 neg.b r3,r3 - test_move_cc 0 0 0 0 + test_cc 0 0 0 1 dumpr3 ; ffffff01 move.d 0x456789ab,r3 neg.b r3,r3 - test_move_cc 0 0 0 0 + test_cc 0 0 0 1 dumpr3 ; 45678955 quit Index: sim/cris/asm/nonvcv32.ms =================================================================== RCS file: sim/cris/asm/nonvcv32.ms diff -N sim/cris/asm/nonvcv32.ms --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/cris/asm/nonvcv32.ms 22 Oct 2007 16:39:39 -0000 @@ -0,0 +1,167 @@ +# mach: crisv32 + + .include "testutils.inc" + +; Check for various non-arithmetic insns that C and V are not affected +; on v32 (where they were on v10), as the generic tests don't cover +; that; they are cleared before testing. + +; First, a macro testing that VC are unaffected, not counting previous +; register contents. + .macro nonvc0 insn op + move.d $r0,$r3 + setf vc + .ifnc \insn,swapnwbr + \insn \op,$r3 + .else + \insn $r3 + .endif + bcc 9f + nop + bvc 9f + nop + move.d $r0,$r3 + clearf vc + .ifnc \insn,swapnwbr + \insn \op,$r3 + .else + \insn $r3 + .endif + bcs 9f + nop + bvc 8f + nop +9: + fail +8: + .endm + +; Use the above, but initialize the non-parameter operand to a value. + .macro nonvc1 insn val op + move.d \val,$r0 + nonvc0 \insn,\op + .endm + +; Use the above, iterating over various values. + .macro nonvc2 insn op + .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 + nonvc1 \insn,\p,\op + nonvc1 \insn,-\p,\op + .endr + .endm + + .macro nonvc2q insn op min=-63 max=63 + .if \op >= \min &&&& \op <= \max + nonvc2 \insn,\op + .endif + .endm + +; The above, for each .b .w .d insn variant. + .macro nonvcbwd insn op + .irp s,.b,.w,.d + nonvc2 \insn\s,\op + .endr + .endm + +; For various insns with register, dword constant and memory operands. + .macro nonvcitermcd op=[$r4] + nonvc2 and.d,\op + nonvc2 move.d,\op + nonvc2 or.d,\op + .endm + +; Similar, for various insns with register, word constant and memory operands. + .macro nonvcitermcw op=[$r4] + nonvcitermcd \op + nonvc2 and.w,\op + nonvc2 move.w,\op + nonvc2 or.w,\op + nonvc2 movs.w,\op + nonvc2 movu.w,\op + .endm + +; Similar, for various insns with register, byte constant and memory operands. + .macro nonvcitermcb op=[$r4] + nonvcitermcw \op + nonvc2 and.b,\op + nonvc2 move.b,\op + nonvc2 or.b,\op + nonvc2 movs.b,\op + nonvc2 movu.b,\op + .endm + +; Similar, for insns with quick constant operands. + .macro nonvciterq op + nonvcitermcb \op + nonvc2 bound.b,\op + nonvc2q andq,\op,min=-32,max=31 + nonvc2q asrq,\op,min=0,max=31 + nonvc2q lsrq,\op,min=0,max=31 + nonvc2q orq,\op,min=-32,max=31 + nonvc2q moveq,\op,min=-32,max=31 + .endm + +; Similar, for insns with register operands. + .macro nonvciterr op + nonvcitermcb \op + nonvcbwd bound,\op + nonvc2 abs,\op + nonvcbwd asr,\op + nonvc2 dstep,\op + nonvcbwd lsr,\op + nonvcbwd lsl,\op + nonvc2 lz,\op + nonvc2 swapnwbr + nonvc2 xor,\op + .endm + +; Test all applicable constant, register and memory variants of a value. + .macro tst op +; Constants + .if (\op <= 31 &&&& \op >= -32) + nonvciterq \op + .elseif (\op <= 255 &&&& \op >= -128) + nonvcitermcb \op + nonvcbwd bound,\op + .elseif (\op <= 65535 &&&& \op >= -32767) + nonvcitermcw \op + nonvc2 bound.w,\op + nonvc2 bound.d,\op + .else + nonvcitermcd \op + nonvc2 bound.d,\op + .endif +; Registers + move.d \op,$r4 + nonvciterr $r4 +; Memory + nonvcitermcb [$r5] + addq 4,$r5 + .section .rodata + .dword \op + .previous + .endm + +; As above but negation too. + .macro tstpm op + tst \op + tst -\op + .endm + + +; Set up for the actual test. + + start + move.d c0,$r5 + + .section .rodata +c0: + .previous + +; Finally, test. + + .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 + tstpm \x + .endr + + pass Index: sim/cris/asm/op3.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/op3.ms,v retrieving revision 1.1 diff -p -u -r1.1 op3.ms --- sim/cris/asm/op3.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/op3.ms 22 Oct 2007 16:39:39 -0000 @@ -43,8 +43,8 @@ x: moveq 0,r5 bdap 2,r10 - test_move_cc 0 0 0 0 movu.b [r3],r5 + test_move_cc 0 0 0 0 dumpr3 ; aa move.d 0x42435567,r8 brgds, H-P