[patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator

[patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator

[Richard Sandiford]

mips.igen's handling of ll, sc and swxc1 is currently hardwired
for WITH_TARGET_WORD_BITSIZE == 64.  The patch below fixes this
by using the same constructs as other loads and stores.  It cures
gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces
no regressions.  OK to install?

Richard


sim/mips/
	* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
	(sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
	shifts for that case.

Index: sim/mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.66
diff -u -p -r1.66 mips.igen
--- sim/mips/mips.igen	14 May 2007 16:24:25 -0000	1.66
+++ sim/mips/mips.igen	2 Oct 2007 16:19:52 -0000
@@ -2263,7 +2263,7 @@
 	  {
 	    unsigned64 memval = 0;
 	    unsigned64 memval1 = 0;
-	    unsigned64 mask = 0x7;
+	    unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
 	    unsigned int shift = 2;
 	    unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
 	    unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
@@ -3199,10 +3199,12 @@
 	  {
 	    unsigned64 memval = 0;
 	    unsigned64 memval1 = 0;
-	    unsigned64 mask = 0x7;
+	    unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+	    address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+	    address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
 	    unsigned int byte;
-	    paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-	    byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+	    paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+	    byte = ((vaddr & mask) ^ bigendiancpu);
 	    memval = ((unsigned64) GPR[RT] << (8 * byte));
 	    if (LLBIT)
 	      {
@@ -5552,10 +5554,12 @@
     {
      unsigned64 memval = 0;
      unsigned64 memval1 = 0;
-     unsigned64 mask = 0x7;
+     unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+     address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+     address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
      unsigned int byte;
-     paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-     byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+     paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+     byte = ((vaddr & mask) ^ bigendiancpu);
      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
       {
        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);

Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator

[Daniel Jacobowitz]

On Tue, Oct 02, 2007 at 05:31:23PM +0100, Richard Sandiford wrote:
> mips.igen's handling of ll, sc and swxc1 is currently hardwired
> for WITH_TARGET_WORD_BITSIZE == 64.  The patch below fixes this
> by using the same constructs as other loads and stores.  It cures
> gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces
> no regressions.  OK to install?
> 
> Richard
> 
> 
> sim/mips/
> 	* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
> 	(sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
> 	shifts for that case.

OK, thanks.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator

[Richard Sandiford]

Daniel Jacobowitz <drow@false.org> writes:
> On Tue, Oct 02, 2007 at 05:31:23PM +0100, Richard Sandiford wrote:
>> mips.igen's handling of ll, sc and swxc1 is currently hardwired
>> for WITH_TARGET_WORD_BITSIZE == 64.  The patch below fixes this
>> by using the same constructs as other loads and stores.  It cures
>> gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces
>> no regressions.  OK to install?
>> 
>> Richard
>> 
>> 
>> sim/mips/
>> 	* mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
>> 	(sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
>> 	shifts for that case.
>
> OK, thanks.

Thanks, installed.