From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23635 invoked by alias); 2 Oct 2007 16:31:33 -0000 Received: (qmail 23617 invoked by uid 22791); 2 Oct 2007 16:31:31 -0000 X-Spam-Check-By: sourceware.org Received: from smtp.nildram.co.uk (HELO smtp.nildram.co.uk) (195.149.33.74) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 02 Oct 2007 16:31:26 +0000 Received: from firetop.home (85-211-25-104.dyn.gotadsl.co.uk [85.211.25.104]) by smtp.nildram.co.uk (Postfix) with ESMTP id 7DECC4ED64 for ; Tue, 2 Oct 2007 17:31:21 +0100 (BST) Received: from richard by firetop.home with local (Exim 4.63) (envelope-from ) id 1IckeZ-0001z0-T2 for gdb-patches@sourceware.org; Tue, 02 Oct 2007 17:31:23 +0100 From: Richard Sandiford To: gdb-patches@sourceware.org Mail-Followup-To: gdb-patches@sourceware.org, rsandifo@nildram.co.uk Subject: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator Date: Tue, 02 Oct 2007 16:31:00 -0000 Message-ID: <87k5q5v5pg.fsf@firetop.home> User-Agent: Gnus/5.110006 (No Gnus v0.6) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00019.txt.bz2 mips.igen's handling of ll, sc and swxc1 is currently hardwired for WITH_TARGET_WORD_BITSIZE == 64. The patch below fixes this by using the same constructs as other loads and stores. It cures gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces no regressions. OK to install? Richard sim/mips/ * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. (sc, swxc1): Likewise. Also fix big-endian and reverse-endian shifts for that case. Index: sim/mips/mips.igen =================================================================== RCS file: /cvs/src/src/sim/mips/mips.igen,v retrieving revision 1.66 diff -u -p -r1.66 mips.igen --- sim/mips/mips.igen 14 May 2007 16:24:25 -0000 1.66 +++ sim/mips/mips.igen 2 Oct 2007 16:19:52 -0000 @@ -2263,7 +2263,7 @@ { unsigned64 memval = 0; unsigned64 memval1 = 0; - unsigned64 mask = 0x7; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); unsigned int shift = 2; unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); @@ -3199,10 +3199,12 @@ { unsigned64 memval = 0; unsigned64 memval1 = 0; - unsigned64 mask = 0x7; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); memval = ((unsigned64) GPR[RT] << (8 * byte)); if (LLBIT) { @@ -5552,10 +5554,12 @@ { unsigned64 memval = 0; unsigned64 memval1 = 0; - unsigned64 mask = 0x7; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); { StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);