From: Daniel Jacobowitz <drow@false.org>
To: gdb-patches@sourceware.org, rsandifo@nildram.co.uk
Subject: Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator
Date: Sun, 07 Oct 2007 04:43:00 -0000 [thread overview]
Message-ID: <20071007044307.GA20114@caradoc.them.org> (raw)
In-Reply-To: <87k5q5v5pg.fsf@firetop.home>
On Tue, Oct 02, 2007 at 05:31:23PM +0100, Richard Sandiford wrote:
> mips.igen's handling of ll, sc and swxc1 is currently hardwired
> for WITH_TARGET_WORD_BITSIZE == 64. The patch below fixes this
> by using the same constructs as other loads and stores. It cures
> gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces
> no regressions. OK to install?
>
> Richard
>
>
> sim/mips/
> * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
> (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
> shifts for that case.
OK, thanks.
--
Daniel Jacobowitz
CodeSourcery
next prev parent reply other threads:[~2007-10-07 4:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-02 16:31 Richard Sandiford
2007-10-07 4:43 ` Daniel Jacobowitz [this message]
2007-10-07 18:41 ` Richard Sandiford
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