From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14206 invoked by alias); 7 Oct 2007 04:43:14 -0000 Received: (qmail 14198 invoked by uid 22791); 7 Oct 2007 04:43:13 -0000 X-Spam-Check-By: sourceware.org Received: from NaN.false.org (HELO nan.false.org) (208.75.86.248) by sourceware.org (qpsmtpd/0.31) with ESMTP; Sun, 07 Oct 2007 04:43:10 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 18676980E0; Sun, 7 Oct 2007 04:43:09 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id C034298001; Sun, 7 Oct 2007 04:43:08 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.67) (envelope-from ) id 1IeNyt-0005Iv-VA; Sun, 07 Oct 2007 00:43:07 -0400 Date: Sun, 07 Oct 2007 04:43:00 -0000 From: Daniel Jacobowitz To: gdb-patches@sourceware.org, rsandifo@nildram.co.uk Subject: Re: [patch] Fix ll, sc and swxc1 for the 32-bit MIPS simulator Message-ID: <20071007044307.GA20114@caradoc.them.org> Mail-Followup-To: gdb-patches@sourceware.org, rsandifo@nildram.co.uk References: <87k5q5v5pg.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87k5q5v5pg.fsf@firetop.home> User-Agent: Mutt/1.5.15 (2007-04-09) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00096.txt.bz2 On Tue, Oct 02, 2007 at 05:31:23PM +0100, Richard Sandiford wrote: > mips.igen's handling of ll, sc and swxc1 is currently hardwired > for WITH_TARGET_WORD_BITSIZE == 64. The patch below fixes this > by using the same constructs as other loads and stores. It cures > gcc.target/mips/atomic-memory-1.c for mipsisa32-elf and introduces > no regressions. OK to install? > > Richard > > > sim/mips/ > * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. > (sc, swxc1): Likewise. Also fix big-endian and reverse-endian > shifts for that case. OK, thanks. -- Daniel Jacobowitz CodeSourcery