[v850 sim] correcting psw flags for divide special cases.

[v850 sim] correcting psw flags for divide special cases.

[DJ Delorie]

2006-04-13  DJ Delorie  <dj@redhat.com>

	* simops.c (OP_2C207E0): Correct PSW flags for special divu
	conditions.
	(OP_2C007E0): Likewise, for div.
	(OP_28207E0): Likewise, for divhu.
	(OP_28007E0): Likewise, for divh.

Index: simops.c
===================================================================
RCS file: /cvs/src/src/sim/v850/simops.c,v
retrieving revision 1.8
diff -p -U3 -r1.8 simops.c
--- simops.c	18 Jan 2004 14:56:40 -0000	1.8
+++ simops.c	13 Apr 2006 23:34:03 -0000
@@ -2264,19 +2264,20 @@ OP_2C207E0 (void)
   
   if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient & 0x80000000) PSW |= PSW_S;
+      if (overflow)      PSW |= PSW_OV;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient & 0x80000000) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2291,7 +2292,6 @@ OP_2C007E0 (void)
   signed long int remainder;
   signed long int divide_by;
   signed long int divide_this;
-  int         overflow = 0;
   
   trace_input ("div", OP_REG_REG_REG, 0);
   
@@ -2300,21 +2300,28 @@ OP_2C007E0 (void)
   divide_by   = State.regs[ OP[0] ];
   divide_this = State.regs[ OP[1] ];
   
-  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
+  if (divide_by == 0)
     {
-      overflow  = 1;
-      divide_by = 1;
+      PSW |= PSW_OV;
     }
+  else if (divide_by == -1 && divide_this == (1 << 31))
+    {
+      PSW &= ~PSW_Z;
+      PSW |= PSW_OV | PSW_S;
+      State.regs[ OP[1] ] = (1 << 31);
+      State.regs[ OP[2] >> 11 ] = 0;
+    }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient <  0) PSW |= PSW_S;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient <  0) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2340,19 +2347,20 @@ OP_28207E0 (void)
   
   if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient & 0x80000000) PSW |= PSW_S;
+      if (overflow)      PSW |= PSW_OV;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient & 0x80000000) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2376,21 +2384,28 @@ OP_28007E0 (void)
   divide_by  = State.regs[ OP[0] ];
   divide_this = EXTEND16 (State.regs[ OP[1] ]);
   
-  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
+  if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else if (divide_by == -1 && divide_this == (1 << 31))
+    {
+      PSW &= ~PSW_Z;
+      PSW |= PSW_OV | PSW_S;
+      State.regs[ OP[1] ] = (1 << 31);
+      State.regs[ OP[2] >> 11 ] = 0;
+    }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient <  0) PSW |= PSW_S;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient <  0) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Thu, Apr 13, 2006 at 07:36:49PM -0400, DJ Delorie wrote:
> 
> 2006-04-13  DJ Delorie  <dj@redhat.com>
> 
> 	* simops.c (OP_2C207E0): Correct PSW flags for special divu
> 	conditions.
> 	(OP_2C007E0): Likewise, for div.
> 	(OP_28207E0): Likewise, for divhu.
> 	(OP_28007E0): Likewise, for divh.

Hi DJ,

The problem with patches without any human-readable text is we don't
know what you expect of them... are you asking for approval?  If so,
I'm not sure why, since you're the m32c sim maintainer and few others
on this list even know what an m32c is.  If you're just posting the
patch as an "FYI, I committed this", then I'd like to point out that
you didn't commit it :-)

-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Fri, Apr 14, 2006 at 04:35:20PM -0400, Daniel Jacobowitz wrote:
> On Thu, Apr 13, 2006 at 07:36:49PM -0400, DJ Delorie wrote:
> > 
> > 2006-04-13  DJ Delorie  <dj@redhat.com>
> > 
> > 	* simops.c (OP_2C207E0): Correct PSW flags for special divu
> > 	conditions.
> > 	(OP_2C007E0): Likewise, for div.
> > 	(OP_28207E0): Likewise, for divhu.
> > 	(OP_28007E0): Likewise, for divh.
> 
> Hi DJ,
> 
> The problem with patches without any human-readable text is we don't
> know what you expect of them... are you asking for approval?  If so,
> I'm not sure why, since you're the m32c sim maintainer and few others
> on this list even know what an m32c is.  If you're just posting the
> patch as an "FYI, I committed this", then I'd like to point out that
> you didn't commit it :-)

Er, this was a v850 patch, not an m32c patch.  D'oh.

Is there anyone out there who can review v850 changes?  If not, I
don't see any reason why you shouldn't check them in.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] correcting psw flags for divide special cases.

[DJ Delorie]

> The problem with patches without any human-readable text is we don't
> know what you expect of them... are you asking for approval?

I can see how that would be confusing.  I will try to remember to add
at least "Ok?"  or "Applied" from now on.

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Mon, Apr 17, 2006 at 03:35:20PM -0400, DJ Delorie wrote:
> 
> > The problem with patches without any human-readable text is we don't
> > know what you expect of them... are you asking for approval?
> 
> I can see how that would be confusing.  I will try to remember to add
> at least "Ok?"  or "Applied" from now on.

Thanks.

In the mean time, would you be willing to be listed as maintainer for
the v850 sim?  I do not believe there is anyone better qualified at
the moment; in fact, I don't see any other way to get v850 patches
reviewed :-)

-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] correcting psw flags for divide special cases.

[DJ Delorie]

> In the mean time, would you be willing to be listed as maintainer
> for the v850 sim?  I do not believe there is anyone better qualified
> at the moment; in fact, I don't see any other way to get v850
> patches reviewed :-)

I hesitate to take on yet another responsibility, if I spread myself
too thin I won't feel right about how much attention I can give to
each area.

Besides, if you look at the ChangeLog you'd see that I'm far from the
most prolific contributor.

Now, if I had a pile of v850 eval boards on my desk (like I do for the
m32c) that would be a different story ;-)

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Mon, Apr 17, 2006 at 04:20:17PM -0400, DJ Delorie wrote:
> 
> > In the mean time, would you be willing to be listed as maintainer
> > for the v850 sim?  I do not believe there is anyone better qualified
> > at the moment; in fact, I don't see any other way to get v850
> > patches reviewed :-)
> 
> I hesitate to take on yet another responsibility, if I spread myself
> too thin I won't feel right about how much attention I can give to
> each area.
> 
> Besides, if you look at the ChangeLog you'd see that I'm far from the
> most prolific contributor.

Yes, but I have to go back two and a half years to find the last patch
that wasn't related to build machinery :-)

How about if we extended the Authorized Committer blurb from
gdb/MAINTAINERS into sim/?

-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] correcting psw flags for divide special cases.

[DJ Delorie]

> Yes, but I have to go back two and a half years to find the last
> patch that wasn't related to build machinery :-)

Nobody said support was pretty.

> How about if we extended the Authorized Committer blurb from
> gdb/MAINTAINERS into sim/?

That would probably be reasonable.  It's not my ability I'm concerned
about, it's available time, so being able to commit patches without
misleading impressions of copious available resources would be
acceptable.

There's probably a number of people in my position, who occasionally
do support outside of their mainstream maintainerships, and have
enough expertise to do so independently, but not enough time to commit
to a maintainership.  A consistent solution to this would be
worthwhile.

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Tue, Apr 18, 2006 at 03:36:07PM -0400, DJ Delorie wrote:
> There's probably a number of people in my position, who occasionally
> do support outside of their mainstream maintainerships, and have
> enough expertise to do so independently, but not enough time to commit
> to a maintainership.  A consistent solution to this would be
> worthwhile.

If only we already had one.... done and done.  It's as simple as
the below.  Does anyone object to this change?  If not, let's do it,
and then you can commit your own v850 fixes.

Index: MAINTAINERS
===================================================================
RCS file: /cvs/src/src/sim/MAINTAINERS,v
retrieving revision 1.17
diff -u -p -r1.17 MAINTAINERS
--- MAINTAINERS	14 Mar 2006 02:37:35 -0000	1.17
+++ MAINTAINERS	20 Apr 2006 13:08:24 -0000
@@ -20,6 +20,9 @@ common		Ben Elliston <bje@gnu.org>
 common		Frank Ch. Eigler <fche@redhat.com>
 *		(target, then global maintainers)
 
+	Authorized committers for particular sims:
+v850		DJ Delorie <dj@redhat.com>
+
 	Past sim maintainers:
 
 mips		Andrew Cagney <ac131313@redhat.com>


-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] correcting psw flags for divide special cases.

[Daniel Jacobowitz]

On Thu, Apr 20, 2006 at 09:09:21AM -0400, Daniel Jacobowitz wrote:
> On Tue, Apr 18, 2006 at 03:36:07PM -0400, DJ Delorie wrote:
> > There's probably a number of people in my position, who occasionally
> > do support outside of their mainstream maintainerships, and have
> > enough expertise to do so independently, but not enough time to commit
> > to a maintainership.  A consistent solution to this would be
> > worthwhile.
> 
> If only we already had one.... done and done.  It's as simple as
> the below.  Does anyone object to this change?  If not, let's do it,
> and then you can commit your own v850 fixes.

No objections, so committed.

DJ, I'm not planning to go back and look at any v850 patches you've
submitted; as far as I'm concerned you can now commit them on your own
authority, and I don't think my looking at them would do any good
anyway.  Let me know if you need eyes on a particular patch.

-- 
Daniel Jacobowitz
CodeSourcery

Re: [v850 sim] REVISED correcting psw flags for divide special cases.

[DJ Delorie]

This adds two more related fixes to the previous ones (the v850 has a
lot of divide instructions) Ok?

2006-04-13  DJ Delorie  <dj@redhat.com>

	* simops.c (OP_2C207E0): Correct PSW flags for special divu
	conditions.
	(OP_2C007E0): Likewise, for div.
	(OP_28207E0): Likewise, for divhu.
	(OP_28007E0): Likewise, for divh.  Also, sign-extend the correct
	operand.
	* v850.igen (divh): Likewise, for 2-op divh.

Index: simops.c
===================================================================
RCS file: /cvs/src/src/sim/v850/simops.c,v
retrieving revision 1.8
diff -p -U3 -r1.8  simops.c
--- simops.c	18 Jan 2004 14:56:40 -0000	1.8
+++ simops.c	18 Apr 2006 19:42:43 -0000
@@ -2264,19 +2264,20 @@ OP_2C207E0 (void)
   
   if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient & 0x80000000) PSW |= PSW_S;
+      if (overflow)      PSW |= PSW_OV;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient & 0x80000000) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2291,7 +2292,6 @@ OP_2C007E0 (void)
   signed long int remainder;
   signed long int divide_by;
   signed long int divide_this;
-  int         overflow = 0;
   
   trace_input ("div", OP_REG_REG_REG, 0);
   
@@ -2300,21 +2300,28 @@ OP_2C007E0 (void)
   divide_by   = State.regs[ OP[0] ];
   divide_this = State.regs[ OP[1] ];
   
-  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
+  if (divide_by == 0)
     {
-      overflow  = 1;
-      divide_by = 1;
+      PSW |= PSW_OV;
     }
+  else if (divide_by == -1 && divide_this == (1 << 31))
+    {
+      PSW &= ~PSW_Z;
+      PSW |= PSW_OV | PSW_S;
+      State.regs[ OP[1] ] = (1 << 31);
+      State.regs[ OP[2] >> 11 ] = 0;
+    }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient <  0) PSW |= PSW_S;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient <  0) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2340,19 +2347,20 @@ OP_28207E0 (void)
   
   if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient & 0x80000000) PSW |= PSW_S;
+      if (overflow)      PSW |= PSW_OV;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient & 0x80000000) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
@@ -2373,24 +2381,31 @@ OP_28007E0 (void)
   
   /* Compute the result.  */
   
-  divide_by  = State.regs[ OP[0] ];
-  divide_this = EXTEND16 (State.regs[ OP[1] ]);
+  divide_by  = EXTEND16 (State.regs[ OP[0] ]);
+  divide_this = State.regs[ OP[1] ];
   
-  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
+  if (divide_by == 0)
     {
-      overflow = 1;
-      divide_by  = 1;
+      PSW |= PSW_OV;
     }
+  else if (divide_by == -1 && divide_this == (1 << 31))
+    {
+      PSW &= ~PSW_Z;
+      PSW |= PSW_OV | PSW_S;
+      State.regs[ OP[1] ] = (1 << 31);
+      State.regs[ OP[2] >> 11 ] = 0;
+    }
+  else
+    {
+      State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
+      State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
-  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
-  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-  
-  /* Set condition codes.  */
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      /* Set condition codes.  */
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
   
-  if (overflow)      PSW |= PSW_OV;
-  if (quotient == 0) PSW |= PSW_Z;
-  if (quotient <  0) PSW |= PSW_S;
+      if (quotient == 0) PSW |= PSW_Z;
+      if (quotient <  0) PSW |= PSW_S;
+    }
   
   trace_output (OP_REG_REG_REG);
 
Index: v850.igen
===================================================================
RCS file: /cvs/src/src/sim/v850/v850.igen,v
retrieving revision 1.7
diff -p -U3 -r1.7  v850.igen
--- v850.igen	5 Sep 2003 17:46:52 -0000	1.7
+++ v850.igen	18 Apr 2006 19:42:43 -0000
@@ -358,28 +358,28 @@ rrrrr!0,000010,RRRRR!0:I:::divh
   
   if (op0 == 0xffffffff && op1 == 0x80000000)
     {
-      result = 0x80000000;
-      ov = 1;
+      PSW &= ~PSW_Z;
+      PSW |= PSW_OV | PSW_S;
+      State.regs[OP[1]] = 0x80000000;
     }
-  else if (op0 != 0)
+  else if (op0 == 0)
     {
-      result = op1 / op0;
-      ov = 0;
+      PSW |= PSW_OV;
     }
   else
     {
-      result = 0x0;
-      ov = 1;
-    }
-  
-  /* Compute the condition codes.  */
-  z = (result == 0);
-  s = (result & 0x80000000);
+      result = op1 / op0;
+      ov = 0;
+
+      /* Compute the condition codes.  */
+      z = (result == 0);
+      s = (result & 0x80000000);
   
-  /* Store the result and condition codes.  */
-  State.regs[OP[1]] = result;
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
+      /* Store the result and condition codes.  */
+      State.regs[OP[1]] = result;
+      PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+      PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
+    }
 
   trace_output (OP_REG_REG);