From: Omair Javaid <omair.javaid@linaro.org>
To: gdb-patches@sourceware.org
Subject: Re: [PATCH v3 2/6] Implement support for recording thumb2 ASIMD struct ld/st insns
Date: Wed, 10 Sep 2014 11:16:00 -0000 [thread overview]
Message-ID: <1410347749-24639-1-git-send-email-omair.javaid@linaro.org> (raw)
In-Reply-To: <CANu=Dmj8PkF0QUc=zT7CED=Fm2S2foH3iB=-ux8BMh-tF9Er3Q@mail.gmail.com>
gdb:
2014-08-13 Omair Javaid <omair.javaid@linaro.org>
* arm-tdep.c (thumb2_record_asimd_struct_ld_st): Add record handler
for advance SIMD struct ld/st insn.
(thumb2_record_decode_insn_handler): Replace stub handler with
thumb2_record_asimd_struct_ld_st.
---
gdb/arm-tdep.c | 191 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 190 insertions(+), 1 deletion(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 21c0242..27136e3 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -13072,6 +13072,195 @@ thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
return arm_record_asimd_vfp_coproc (thumb2_insn_r);
}
+/* Record handler for advance SIMD structure load/store instructions. */
+
+static int
+thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
+{
+ struct regcache *reg_cache = thumb2_insn_r->regcache;
+ uint32_t l_bit, a_bit, b_bits;
+ uint32_t record_buf[128], record_buf_mem[128];
+ uint32_t reg_rn, reg_vd, address, f_esize, f_elem;
+ uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
+ uint8_t f_ebytes;
+
+ l_bit = bit (thumb2_insn_r->arm_insn, 21);
+ a_bit = bit (thumb2_insn_r->arm_insn, 23);
+ b_bits = bits (thumb2_insn_r->arm_insn, 8, 11);
+ reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+ reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
+ reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
+ f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7));
+ f_esize = 8 * f_ebytes;
+ f_elem = 8 / f_ebytes;
+
+ if (!l_bit)
+ {
+ ULONGEST u_regval = 0;
+ regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
+ address = u_regval;
+
+ if (!a_bit)
+ {
+ /* Handle VST1. */
+ if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
+ {
+ if (b_bits == 0x07)
+ bf_regs = 1;
+ else if (b_bits == 0x0a)
+ bf_regs = 2;
+ else if (b_bits == 0x06)
+ bf_regs = 3;
+ else if (b_bits == 0x02)
+ bf_regs = 4;
+ else
+ bf_regs = 0;
+
+ for (index_r = 0; index_r < bf_regs; index_r++)
+ {
+ for (index_e = 0; index_e < f_elem; index_e++)
+ {
+ record_buf_mem[index_m++] = f_ebytes;
+ record_buf_mem[index_m++] = address;
+ address = address + f_ebytes;
+ thumb2_insn_r->mem_rec_count += 1;
+ }
+ }
+ }
+ /* Handle VST2. */
+ else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
+ {
+ if (b_bits == 0x09 || b_bits == 0x08)
+ bf_regs = 1;
+ else if (b_bits == 0x03)
+ bf_regs = 2;
+ else
+ bf_regs = 0;
+
+ for (index_r = 0; index_r < bf_regs; index_r++)
+ for (index_e = 0; index_e < f_elem; index_e++)
+ {
+ for (loop_t = 0; loop_t < 2; loop_t++)
+ {
+ record_buf_mem[index_m++] = f_ebytes;
+ record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
+ thumb2_insn_r->mem_rec_count += 1;
+ }
+ address = address + (2 * f_ebytes);
+ }
+ }
+ /* Handle VST3. */
+ else if ((b_bits & 0x0e) == 0x04)
+ {
+ for (index_e = 0; index_e < f_elem; index_e++)
+ {
+ for (loop_t = 0; loop_t < 3; loop_t++)
+ {
+ record_buf_mem[index_m++] = f_ebytes;
+ record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
+ thumb2_insn_r->mem_rec_count += 1;
+ }
+ address = address + (3 * f_ebytes);
+ }
+ }
+ /* Handle VST4. */
+ else if (!(b_bits & 0x0e))
+ {
+ for (index_e = 0; index_e < f_elem; index_e++)
+ {
+ for (loop_t = 0; loop_t < 4; loop_t++)
+ {
+ record_buf_mem[index_m++] = f_ebytes;
+ record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
+ thumb2_insn_r->mem_rec_count += 1;
+ }
+ address = address + (4 * f_ebytes);
+ }
+ }
+ }
+ else
+ {
+ uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11);
+
+ if (bft_size == 0x00)
+ f_ebytes = 1;
+ else if (bft_size == 0x01)
+ f_ebytes = 2;
+ else if (bft_size == 0x02)
+ f_ebytes = 4;
+ else
+ f_ebytes = 0;
+
+ /* Handle VST1. */
+ if (!(b_bits & 0x0b) || b_bits == 0x08)
+ thumb2_insn_r->mem_rec_count = 1;
+ /* Handle VST2. */
+ else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
+ thumb2_insn_r->mem_rec_count = 2;
+ /* Handle VST3. */
+ else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
+ thumb2_insn_r->mem_rec_count = 3;
+ /* Handle VST4. */
+ else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
+ thumb2_insn_r->mem_rec_count = 4;
+
+ for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++)
+ {
+ record_buf_mem[index_m] = f_ebytes;
+ record_buf_mem[index_m] = address + (index_m * f_ebytes);
+ }
+ }
+ }
+ else
+ {
+ if (!a_bit)
+ {
+ /* Handle VLD1. */
+ if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
+ thumb2_insn_r->reg_rec_count = 1;
+ /* Handle VLD2. */
+ else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
+ thumb2_insn_r->reg_rec_count = 2;
+ /* Handle VLD3. */
+ else if ((b_bits & 0x0e) == 0x04)
+ thumb2_insn_r->reg_rec_count = 3;
+ /* Handle VLD4. */
+ else if (!(b_bits & 0x0e))
+ thumb2_insn_r->reg_rec_count = 4;
+ }
+ else
+ {
+ /* Handle VLD1. */
+ if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
+ thumb2_insn_r->reg_rec_count = 1;
+ /* Handle VLD2. */
+ else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
+ thumb2_insn_r->reg_rec_count = 2;
+ /* Handle VLD3. */
+ else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
+ thumb2_insn_r->reg_rec_count = 3;
+ /* Handle VLD4. */
+ else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
+ thumb2_insn_r->reg_rec_count = 4;
+
+ for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++)
+ record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;
+ }
+ }
+
+ if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15)
+ {
+ record_buf[index_r] = reg_rn;
+ thumb2_insn_r->reg_rec_count += 1;
+ }
+
+ REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+ record_buf);
+ MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+ record_buf_mem);
+ return 0;
+}
+
/* Decodes thumb2 instruction type and invokes its record handler. */
static unsigned int
@@ -13134,7 +13323,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
else if (!((op2 & 0x71) ^ 0x10))
{
/* Advanced SIMD or structure load/store instructions. */
- return arm_record_unsupported_insn (thumb2_insn_r);
+ return thumb2_record_asimd_struct_ld_st (thumb2_insn_r);
}
else if (!((op2 & 0x67) ^ 0x01))
{
--
1.9.1
next prev parent reply other threads:[~2014-09-10 11:16 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-13 13:13 [PATCH v3 0/6] ARM process record/replay improvements Omair Javaid
2014-08-13 13:13 ` [PATCH v3 6/6] Fix reverse-step and reverse-next over undebuggable solib code Omair Javaid
2014-08-27 9:09 ` Omair Javaid
2014-08-27 10:34 ` Pedro Alves
2014-08-13 13:13 ` [PATCH v3 1/6] Implements support for recording arm/thumb mode coprocessor instructions Omair Javaid
2014-08-13 14:10 ` Will Newton
2014-08-27 9:07 ` Omair Javaid
2014-08-27 10:05 ` Pedro Alves
2014-08-28 9:50 ` [PATCH] Implement " Omair Javaid
2014-09-02 14:51 ` Will Newton
2014-08-13 13:13 ` [PATCH v3 4/6] Implement support for recording extension register ld/st insn Omair Javaid
2014-08-13 14:10 ` Will Newton
2014-08-27 9:21 ` Omair Javaid
2014-08-27 10:17 ` Pedro Alves
2014-08-28 12:56 ` Omair Javaid
2014-09-02 14:59 ` Will Newton
2014-09-10 11:29 ` Omair Javaid
2014-09-10 11:55 ` Will Newton
2014-08-13 13:13 ` [PATCH v3 2/6] Implements support for recording thumb2 ASIMD struct " Omair Javaid
2014-08-13 14:10 ` Will Newton
2014-08-27 9:08 ` Omair Javaid
2014-08-27 10:09 ` Pedro Alves
2014-08-28 10:56 ` [PATCH v3 2/6] Implement support for recording thumb2 ASIMD struct ld/st insns Omair Javaid
2014-09-02 14:55 ` Will Newton
2014-09-10 11:16 ` Omair Javaid [this message]
2014-09-10 11:54 ` Will Newton
2014-08-13 13:13 ` [PATCH v3 3/6] Implement support for recording VFP data processing instructions Omair Javaid
2014-08-13 14:10 ` Will Newton
2014-08-27 9:10 ` Omair Javaid
2014-08-27 10:11 ` Pedro Alves
2014-08-28 11:06 ` Omair Javaid
2014-08-13 13:13 ` [PATCH v3 5/6] Implement support for recording vector data transfer instructions Omair Javaid
2014-08-13 14:10 ` Will Newton
2014-08-27 9:09 ` Omair Javaid
2014-08-27 10:19 ` Pedro Alves
2014-08-28 13:07 ` Omair Javaid
2014-08-27 9:05 ` [PATCH v3 0/6] ARM process record/replay improvements Omair Javaid
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