* MIPS32 / MIPS64 release 2 support in simulator
@ 2004-11-03 15:26 David Ung
[not found] ` <mailpost.1099495587.2562@news-sj1-1>
0 siblings, 1 reply; 21+ messages in thread
From: David Ung @ 2004-11-03 15:26 UTC (permalink / raw)
To: gdb-patches
The following file is for MIPS32 / MIPS64 release 2 extensions to the
simulator.
David.
2004-11-03 David Ung <davidu@mips.com>
* mips.igen: Added include of m3264r2.igen file.
* m3264r2.igen: New file. New instructions for mips32r2 and mips64r2.
Index: mips.igen
===================================================================
RCS file: /cvs/uberbaum/sim/mips/mips.igen,v
retrieving revision 1.57
diff -c -r1.57 mips.igen
*** mips.igen 10 Apr 2004 06:51:49 -0000 1.57
--- mips.igen 3 Nov 2004 15:17:41 -0000
***************
*** 5258,5263 ****
--- 5258,5264 ----
:include:::m16.igen
:include:::mdmx.igen
:include:::mips3d.igen
+ :include:::m3264r2.igen
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
Index: m3264r2.igen
===================================================================
// -*- C -*-
//
// MIPS32 / MIPS64 release 2 extensions
//
// TBD: wrpgr, rdpgr, rdhwr
010000,01011,5.RT,01100,00000,0,00,000::32::DI
"di":RT == 0
"di r<RT>"
*mips32,mips64:
{
GPR[RT] = SR;
SR &= ~1;
TRACE_ALU_RESULT1 (GPR[RT]);
}
010000,01011,5.RT,01100,00000,1,00,000::32::EI
"ei":RT == 0
"ei r<RT>"
*mips32,mips64:
{
GPR[RT] = SR;
SR |= 1;
TRACE_ALU_RESULT1 (GPR[RT]);
}
000001,5.BASE,11111,16.OFFSET::32::SYNCI
"synci <OFFSET>(r<BASE>)"
*mips32,mips64:
{
// sync i-cache - nothing to do currently
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
"ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips32,mips64:
{
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB));
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips64:
{
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
*mips64:
{
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
*mips64:
{
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips32,mips64:
{
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] = EXTEND32 (GPR[RT] ^
((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB)));
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips64:
{
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
*mips64:
{
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB + 32)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
*mips64:
{
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32)))
& MASK64 (MSB + 32, LSB + 32);
TRACE_ALU_RESULT1 (GPR[RT]);
}
000000,00001,5.RT,5.RD,5.SA,111010::64::DROTR
"drotr r<RD>, r<RT>, <SA>"
*mips64:
{
TRACE_ALU_INPUT2 (GPR[RT], SA);
GPR[RD] = ROTR64 (GPR[RT], SA);
TRACE_ALU_RESULT1 (GPR[RD]);
}
000000,00001,5.RT,5.RD,5.SA,111110::64::DROTR32
"drotr32 r<RD>, r<RT>, <SA>"
*mips64:
{
TRACE_ALU_INPUT2 (GPR[RT], SA);
GPR[RD] = ROTR64 (GPR[RT], SA + 32);
TRACE_ALU_RESULT1 (GPR[RD]);
}
000000,00001,5.RT,5.RD,5.SA,000010::32::ROTR
"rotr r<RD>, r<RT>, <SA>"
*mips32,mips64:
{
TRACE_ALU_INPUT2 (GPR[RT], SA);
GPR[RD] = EXTEND32 (ROTR32 (GPR[RT], SA));
TRACE_ALU_RESULT1 (GPR[RD]);
}
000000,5.RS,5.RT,5.RD,00001,010110::64::DROTRV
"drotrv r<RD>, r<RT>, r<RS>"
*mips64:
{
TRACE_ALU_INPUT2 (GPR[RT], GPR[RS]);
GPR[RD] = ROTR64 (GPR[RT], GPR[RS] & 0x3f);
TRACE_ALU_RESULT1 (GPR[RD]);
}
000000,5.RS,5.RT,5.RD,00001,000110::32::ROTRV
"rotrv r<RD>, r<RT>, r<RS>"
*mips32,mips64:
{
TRACE_ALU_INPUT2 (GPR[RT], GPR[RS]);
GPR[RD] = EXTEND32 (ROTR32 (GPR[RT], GPR[RS] & 0x1f));
TRACE_ALU_RESULT1 (GPR[RD]);
}
011111,00000,5.RT,5.RD,00010,100100::64::DSBH
"dsbh r<RD>, r<RT>"
*mips64:
{
union { unsigned64 d; unsigned16 h[4]; } u;
TRACE_ALU_INPUT1 (GPR[RT]);
u.d = GPR[RT];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
u.h[2] = SWAP_2 (u.h[2]);
u.h[3] = SWAP_2 (u.h[3]);
GPR[RD] = u.d;
TRACE_ALU_RESULT1 (GPR[RD]);
}
011111,00000,5.RT,5.RD,00101,100100::64::DSHD
"dshd r<RD>, r<RT>"
*mips64:
{
unsigned64 d;
TRACE_ALU_INPUT1 (GPR[RT]);
d = GPR[RT];
GPR[RD] = ((d >> 48)
| (d << 48)
| ((d >> 16) & 0xffff0000)
| ((d & 0xffff0000) << 16));
TRACE_ALU_RESULT1 (GPR[RD]);
}
011111,00000,5.RT,5.RD,00010,100000::32::WSBH
"wsbh r<RD>, r<RT>"
*mips32,mips64:
{
union { unsigned32 w; unsigned16 h[2]; } u;
TRACE_ALU_INPUT1 (GPR[RT]);
u.w = GPR[RT];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
GPR[RD] = EXTEND32 (u.w);
TRACE_ALU_RESULT1 (GPR[RD]);
}
011111,00000,5.RT,5.RD,10000,100000::32::SEB
"seb r<RD>, r<RT>"
*mips32,mips64:
{
TRACE_ALU_INPUT1 (GPR[RT]);
GPR[RD] = EXTEND8 (GPR[RT]);
TRACE_ALU_RESULT1 (GPR[RD]);
}
011111,00000,5.RT,5.RD,11000,100000::32::SEH
"seh r<RD>, r<RT>"
*mips32,mips64:
{
TRACE_ALU_INPUT1 (GPR[RT]);
GPR[RD] = EXTEND16 (GPR[RT]);
TRACE_ALU_RESULT1 (GPR[RD]);
}
010001,00011,5.RT,5.FS,00000000000:COP1Sa:32::MFHC1
"mfhc1 r<RT>, f<FS>"
*mips32,mips64:
{
if (SizeFGR() == 64)
GPR[RT] = EXTEND32 (WORD64HI (FGR[FS]));
else if ((FS & 0x1) == 0)
GPR[RT] = EXTEND32 (FGR[FS + 1]);
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
(long) CIA);
GPR[RT] = EXTEND32 (0xBADF00D);
}
}
010001,00111,5.RT,5.FS,00000000000:COP1Sa:32::MTHC1
"mthc1 r<RT>, f<FS>"
*mips32,mips64:
{
if (SizeFGR() == 64)
StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS]));
else if ((FS & 0x1) == 0)
StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
(long) CIA);
StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE);
}
}
^ permalink raw reply [flat|nested] 21+ messages in thread[parent not found: <mailpost.1099495587.2562@news-sj1-1>]
* Re: MIPS32 / MIPS64 release 2 support in simulator [not found] ` <mailpost.1099495587.2562@news-sj1-1> @ 2004-11-03 16:54 ` cgd 2004-11-03 16:57 ` cgd 1 sibling, 0 replies; 21+ messages in thread From: cgd @ 2004-11-03 16:54 UTC (permalink / raw) To: davidu; +Cc: gdb-patches, cagney [-- Attachment #1: Type: text/plain, Size: 2748 bytes --] Andrew (or somebody), could you please confirm that their assignment is in place? (I don't have access to anything that would let me check easily, as far as I know.) At Wed, 3 Nov 2004 15:26:27 +0000 (UTC), "David Ung" wrote: > The following file is for MIPS32 / MIPS64 release 2 extensions to the > simulator. Based on the way other bits are done: * these should be placed in mips.igen proper (since they're part of a standard MIPS ISA level). If you'd like to try dissuade me from this position, I'm willing to discuss it. But right now, all *other* standard MIPS ISA bits are in mips.igen itself. * the lines like: *mips32,mips64: should be two separate lines. Also: * If you can't provide diffs for new files, at least provide them as an attachment. (If you're interested in faking out CVS so you can provide the diffs easily, see the attached script.) Otherwise, I have fears about whitespace and/or line wrapping. * If you do convince me that a new .igen file is appropriate, you'll need to put an appropriate copyright notice and license on it. I'd suggest starting with the one on, say, mips3d.igen. * You need testsuite coverage for all of the new instructions, please. * Please carefully review the instruction implementations against the manuals, and against the defines and functions already provided by the simulator. Right now, there are some issues. For instance: * DI, EI should sign extend the result, and should use status_IE rather than '1'. * I believe you should be using TRACE_ALU_INPUT0 in DI, EI and in possibly similar places. * you are missing letters in wrpgpr and rdpgpr in comment. * in dshd, I get what you're trying to do, but the code should be less complex to do it. (in particular, the use of the 0xffff0000 masks is confusing). Just write the code the obvious way. 8-) * should use check_fpu in FPU ops, and I believe you should be using check_u64 in the 64-bit ops. Also, appropriate use of NotWordValue would be good. * should probably just move the ror/rorv instructions from vr.igen into mips.igen, and use them since they are as far as I know otherwise the same. Yes, I know they don't print out w/ the official MIPS mnemonics, but the assembler recognizes both and, well, uh, MIPS named them last. 8-) There may be more, those are just the things I noticed on a quick read-through. (Obviously, I'll have to review any updated patch.) (We did an implementation of r2, too, but I've never had time to submit it back. *sigh* Now *I* get to lose on the merge. 8-) chris [-- Attachment #2: fakeadd --] [-- Type: application/octet-stream, Size: 666 bytes --] #!/bin/sh if [ $# -eq 0 ]; then echo "usage: $0 file ..." 1>&2 exit 1 fi if [ -d CVS ]; then :; else echo "$0: fatal error: no CVS directory! exit 1 fi if [ -f CVS/Entries ] && [ -w CVS/Entries ]; then :; else echo "$0: fatal error: CVS/Entries file not writable! exit 1 fi rv=0 for file in "$@"; do if [ -f "$file" ]; then :; else echo "$0: error: \"$file\" does not exist or is not a plain file" rv=1 continue fi if grep "^/$file/" CVS/Entries > /dev/null 2>&1; then echo "$0: error: \"$file\" is already listed in CVS/Entries" rv=1 continue fi echo "/$file/0/dummy timestamp//" >> CVS/Entries echo "$0: added \"$file\"" done exit $rv ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator [not found] ` <mailpost.1099495587.2562@news-sj1-1> 2004-11-03 16:54 ` cgd @ 2004-11-03 16:57 ` cgd [not found] ` <mailpost.1099501062.5136@news-sj1-1> 1 sibling, 1 reply; 21+ messages in thread From: cgd @ 2004-11-03 16:57 UTC (permalink / raw) To: davidu; +Cc: gdb-patches Oh, sorry, missed some very very important things: > *mips32,mips64: These **must** be ...r2 or similar. Otherwise, they'll be included in mips32/mip64 sims. You *are* going to add a configuration that uses them, right? (I don't think we should accept this stuff until you're ready to do so. But it should be very easy to add a generic set of 'r2' configurations.) chris ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <mailpost.1099501062.5136@news-sj1-1>]
* Re: MIPS32 / MIPS64 release 2 support in simulator [not found] ` <mailpost.1099501062.5136@news-sj1-1> @ 2004-11-03 19:01 ` cgd 2004-11-04 13:53 ` David Ung 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2004-11-03 19:01 UTC (permalink / raw) To: davidu; +Cc: gdb-patches At Wed, 3 Nov 2004 16:57:42 +0000 (UTC), cgd@broadcom.com wrote: > > *mips32,mips64: > > These **must** be ...r2 or similar. Otherwise, they'll be included in > mips32/mip64 sims. So, more information about this: this ties in to where the new instructions are located. If we consider this a new ISA -- as the rest of the tools do, and as I think we probably want to do as well -- then: * the new instructions should go into mips.igen. * **all** instructions which are applicable to mips32r2/mips64r2 must be tagged with *mips64r2: and *mips32r2:. If we consider this as an ASE, then: * the new instructions should go into a new file, and * only the new instructions should be tagged with *mips64r2: and *mips32r2:. My personal incliation is that it should be treated as an ISA, just like MIPS32 and MIPS64 were (rather than as being additions to MIPS II or MIPS IV). If you disagree, i'm open to hearing arguments for your position. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-03 19:01 ` cgd @ 2004-11-04 13:53 ` David Ung [not found] ` <mailpost.1099576418.9773@news-sj1-1> 0 siblings, 1 reply; 21+ messages in thread From: David Ung @ 2004-11-04 13:53 UTC (permalink / raw) To: cgd; +Cc: gdb-patches, nigel On Wed, 2004-11-03 at 18:46, cgd@broadcom.com wrote: > At Wed, 3 Nov 2004 16:57:42 +0000 (UTC), cgd@broadcom.com wrote: > > > *mips32,mips64: > > > > These **must** be ...r2 or similar. Otherwise, they'll be included in > > mips32/mip64 sims. > > So, more information about this: this ties in to where the new > instructions are located. > > If we consider this a new ISA -- as the rest of the tools do, and as I > think we probably want to do as well -- then: > > * the new instructions should go into mips.igen. > > * **all** instructions which are applicable to > mips32r2/mips64r2 must be tagged with *mips64r2: and > *mips32r2:. > > If we consider this as an ASE, then: > > * the new instructions should go into a new file, and > > * only the new instructions should be tagged with *mips64r2: > and *mips32r2:. > > > My personal incliation is that it should be treated as an ISA, just > like MIPS32 and MIPS64 were (rather than as being additions to MIPS II > or MIPS IV). > > If you disagree, i'm open to hearing arguments for your position. Agree.. I shall update mips.igen with the new r2 instructions and then submit it as a patch. David. ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <mailpost.1099576418.9773@news-sj1-1>]
* Re: MIPS32 / MIPS64 release 2 support in simulator [not found] ` <mailpost.1099576418.9773@news-sj1-1> @ 2004-11-04 17:46 ` cgd 2004-11-08 16:44 ` Andrew Cagney 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2004-11-04 17:46 UTC (permalink / raw) To: davidu; +Cc: gdb-patches, nigel At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: > I shall update mips.igen with the new r2 instructions and then submit it > as a patch. cool, thanks. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-04 17:46 ` cgd @ 2004-11-08 16:44 ` Andrew Cagney 2004-11-08 18:06 ` David Ung 0 siblings, 1 reply; 21+ messages in thread From: Andrew Cagney @ 2004-11-08 16:44 UTC (permalink / raw) To: cgd, davidu; +Cc: gdb-patches, nigel cgd@broadcom.com wrote: > At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: > >>I shall update mips.igen with the new r2 instructions and then submit it >>as a patch. > > > cool, thanks. Don't. These new changes go in a new file, and that file gets a very clear FSF copyright. Andrew ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-08 16:44 ` Andrew Cagney @ 2004-11-08 18:06 ` David Ung 2004-11-09 15:54 ` David Ung 2004-11-09 16:12 ` Andrew Cagney 0 siblings, 2 replies; 21+ messages in thread From: David Ung @ 2004-11-08 18:06 UTC (permalink / raw) To: Andrew Cagney; +Cc: cgd, gdb-patches, nigel On Mon, 2004-11-08 at 16:43, Andrew Cagney wrote: > cgd@broadcom.com wrote: > > At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: > > > >>I shall update mips.igen with the new r2 instructions and then submit it > >>as a patch. > > > > > > cool, thanks. > > Don't. These new changes go in a new file, and that file gets a very > clear FSF copyright. > > Andrew > arhh. Chris's argument of that the rest of the tools consider rev 2 instructions as an ISA is quite a valid one. And for consistency with the existing structure, it looks to be the right thing to do. But when I got to merging in the r2 instructions into mips.igen, I do see that for every mips32 / 64 instruction, I now have to also tag them mips32r2 / 64r2. It would probably be nicer to just tell it to include all the mips32 instructions (which would be like treating it as an ASE). But then again it brings us back to the original argument, and I probably would lean slightly towards the ISA model and be part of mips.igen depite polluting the whole file with *mips32r2: and *mips64r2: tags. David. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-08 18:06 ` David Ung @ 2004-11-09 15:54 ` David Ung 2004-11-09 16:12 ` Andrew Cagney 1 sibling, 0 replies; 21+ messages in thread From: David Ung @ 2004-11-09 15:54 UTC (permalink / raw) To: Andrew Cagney; +Cc: cgd, gdb-patches, nigel On Mon, 2004-11-08 at 18:06, David Ung wrote: > On Mon, 2004-11-08 at 16:43, Andrew Cagney wrote: > > cgd@broadcom.com wrote: > > > At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: > > > > > >>I shall update mips.igen with the new r2 instructions and then submit it > > >>as a patch. > > > > > > > > > cool, thanks. > > > > Don't. These new changes go in a new file, and that file gets a very > > clear FSF copyright. > > > > Andrew > > > > arhh. Chris's argument of that the rest of the tools consider rev 2 > instructions as an ISA is quite a valid one. And for consistency with > the existing structure, it looks to be the right thing to do. > But when I got to merging in the r2 instructions into mips.igen, I do > see that for every mips32 / 64 instruction, I now have to also tag them > mips32r2 / 64r2. It would probably be nicer to just tell it to include > all the mips32 instructions (which would be like treating it as an > ASE). > But then again it brings us back to the original argument, and I > probably would lean slightly towards the ISA model and be part of > mips.igen depite polluting the whole file with *mips32r2: and *mips64r2: > tags. > > David. > For now, I am assuming we are going for the all in one mips.igen approach. So here is the new patch for release 2 instructions. David. Index: ChangeLog =================================================================== RCS file: /cvs/uberbaum/sim/mips/ChangeLog,v retrieving revision 1.109 diff -c -p -r1.109 ChangeLog *** ChangeLog 24 Sep 2004 20:28:24 -0000 1.109 --- ChangeLog 9 Nov 2004 15:49:51 -0000 *************** *** 1,3 **** --- 1,16 ---- + 2004-11-09 David Ung <davidu@mips.com> + + * mips.igen (mips64r2:): Added models mips32r2 and mips64r2. Tag + all existing instructions which are applicable to + mips32r2/mips64r2, and add new release 2 instructions. + + * vr.igen: The following instructions: ror, rorv, dror, dror32, + drorv and their corresponding worker functions do_ror/dodror are + moved into mips.igen. + + * configure.in: Add targets mipsisa32r2*-*-* and mipsisa64r2*-*-* + to use mips32r2/64r2 models. + 2004-09-24 Monika Chaddha <monika@acmet.com> Committed by Andrew Cagney. Index: configure.in =================================================================== RCS file: /cvs/uberbaum/sim/mips/configure.in,v retrieving revision 1.8 diff -c -p -r1.8 configure.in *** configure.in 19 Aug 2004 07:02:04 -0000 1.8 --- configure.in 9 Nov 2004 15:49:51 -0000 *************** case "${target}" in *** 141,146 **** --- 141,151 ---- sim_igen_filter="32,64,f" sim_m16_filter="16" ;; + mipsisa32r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips32r2" + sim_igen_filter="32,f" + sim_mach_default="mipsisa32r2" + ;; mipsisa32*-*-*) sim_gen=IGEN sim_igen_machine="-M mips32" sim_igen_filter="32,f" *************** case "${target}" in *** 151,156 **** --- 156,166 ---- sim_igen_filter="32,64,f" sim_mach_default="mips_sb1" ;; + mipsisa64r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips64r2,mips3d" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64r2" + ;; mipsisa64*-*-*) sim_gen=IGEN sim_igen_machine="-M mips64,mips3d" sim_igen_filter="32,64,f" Index: mips.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/mips.igen,v retrieving revision 1.57 diff -c -p -r1.57 mips.igen *** mips.igen 10 Apr 2004 06:51:49 -0000 1.57 --- mips.igen 9 Nov 2004 15:49:52 -0000 *************** *** 45,51 **** --- 45,53 ---- :model:::mipsIV:mips8000: :model:::mipsV:mipsisaV: :model:::mips32:mipsisa32: + :model:::mips32r2:mipsisa32r2: :model:::mips64:mipsisa64: + :model:::mips64r2:mipsisa64r2: // Vendor ISAs: // *************** *** 132,137 **** --- 134,140 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 141,146 **** --- 144,150 ---- :function:::address_word:loadstore_ea:address_word base, address_word offset *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ /* If in user mode and UX is not set, use 32-bit compatibility effective *************** *** 178,183 **** --- 182,188 ---- :function:::int:not_word_value:unsigned_word value *mips32: + *mips32r2: { /* On MIPS32, since registers are 32-bits, there's no check to be done. */ return 0; *************** *** 185,190 **** --- 190,196 ---- :function:::int:not_word_value:unsigned_word value *mips64: + *mips64r2: { return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); } *************** *** 212,218 **** --- 218,226 ---- :function:::void:unpredictable: *mips32: + *mips32r2: *mips64: + *mips64r2: { unpredictable_action (CPU, CIA); } *************** *** 300,306 **** --- 308,316 ---- :function:::int:check_mt_hilo:hilo_history *history *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { signed64 time = sim_events_time (SD); *************** *** 322,328 **** --- 332,340 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 392,398 **** --- 404,412 ---- :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { /* FIXME: could record the fact that a stall occured if we want */ *************** *** 445,451 **** --- 459,467 ---- :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: { signed64 time = sim_events_time (SD); hi->op.timestamp = time; *************** *** 468,479 **** --- 484,498 ---- *mipsV: *vr4100: *vr5000: + *vr5400: + *vr5500: { // The check should be similar to mips64 for any with PX/UX bit equivalents. } :function:::void:check_u64:instruction_word insn *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ if (UserMode && (SR & (status_UX|status_PX)) == 0) *************** *** 486,492 **** // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32, mips64) // --- 505,511 ---- // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) // *************** *** 499,505 **** --- 518,526 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 525,531 **** --- 546,554 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 560,566 **** --- 583,591 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 587,593 **** --- 612,620 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 612,618 **** --- 639,647 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 630,636 **** --- 659,667 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 650,656 **** --- 681,689 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 671,677 **** --- 704,712 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 695,701 **** --- 730,738 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 717,723 **** --- 754,762 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 741,747 **** --- 780,788 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 769,775 **** --- 810,818 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 793,799 **** --- 836,844 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 814,820 **** --- 859,867 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 840,846 **** --- 887,895 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 863,869 **** --- 912,920 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 887,893 **** --- 938,946 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 909,915 **** --- 962,970 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 935,941 **** --- 990,998 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 961,967 **** --- 1018,1026 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 987,993 **** --- 1046,1054 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1008,1014 **** --- 1069,1077 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1032,1038 **** --- 1095,1103 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1068,1074 **** --- 1133,1141 ---- 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO "clo r<RD>, r<RS>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1093,1099 **** --- 1160,1168 ---- 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ "clz r<RD>, r<RS>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1121,1126 **** --- 1190,1196 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1142,1147 **** --- 1212,1218 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1170,1175 **** --- 1241,1247 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1192,1197 **** --- 1264,1270 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1204,1209 **** --- 1277,1283 ---- 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO "dclo r<RD>, r<RS>" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1228,1233 **** --- 1302,1308 ---- 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ "dclz r<RD>, r<RS>" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1285,1290 **** --- 1360,1366 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1325,1330 **** --- 1401,1407 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1332,1338 **** --- 1409,1489 ---- do_ddivu (SD_, RS, RT); } + 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT + "dext r<RT>, r<RS>, <LSB>, <SIZE+1>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM + "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU + "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 010000,01011,5.RT,01100,00000,0,00,000::32::DI + "di":RT == 0 + "di r<RT>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR &= ~status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS + "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM + "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB + 32) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU + "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>" + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) + & MASK64 (MSB + 32, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); + } :function:::void:do_div:int rs, int rt { *************** *** 1368,1374 **** --- 1519,1527 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1407,1413 **** --- 1560,1568 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1416,1422 **** } - :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p { unsigned64 lo; --- 1571,1576 ---- *************** *** 1488,1493 **** --- 1642,1648 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1516,1521 **** --- 1671,1677 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1531,1536 **** --- 1687,1767 ---- do_dmultu (SD_, RS, RT, RD); } + + :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y + { + unsigned64 result; + + y &= 63; + TRACE_ALU_INPUT2 (x, y); + result = ROTR64 (x, y); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR + "dror r<RD>, r<RT>, <SHIFT>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 + "dror32 r<RD>, r<RT>, <SHIFT>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); + } + + 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV + "drorv r<RD>, r<RT>, r<RS>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); + } + + + 011111,00000,5.RT,5.RD,00010,100100::64::DSBH + "dsbh r<RD>, r<RT>" + *mips64r2: + { + union { unsigned64 d; unsigned16 h[4]; } u; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + u.d = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + u.h[2] = SWAP_2 (u.h[2]); + u.h[3] = SWAP_2 (u.h[3]); + GPR[RD] = u.d; + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 011111,00000,5.RT,5.RD,00101,100100::64::DSHD + "dshd r<RD>, r<RT>" + *mips64r2: + { + unsigned64 d; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + d = GPR[RT]; + GPR[RD] = ((d >> 48) + | (d << 48) + | ((d & 0x0000ffff00000000) >> 16) + | ((d & 0x00000000ffff0000) << 16)); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + :function:::void:do_dsll:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); *************** *** 1544,1549 **** --- 1775,1781 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1558,1563 **** --- 1790,1796 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1582,1587 **** --- 1815,1821 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1603,1608 **** --- 1837,1843 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1617,1622 **** --- 1852,1858 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1642,1647 **** --- 1878,1884 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1663,1668 **** --- 1900,1906 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1677,1682 **** --- 1915,1921 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1704,1709 **** --- 1943,1949 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1718,1723 **** --- 1958,1964 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1745,1750 **** --- 1986,1992 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1753,1758 **** --- 1995,2037 ---- } + 010000,01011,5.RT,01100,00000,1,00,000::32::EI + "ei":RT == 0 + "ei r<RT>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR |= status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); + } + + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT + "ext r<RT>, r<RS>, <LSB>, <SIZE+1>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + + 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS + "ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] = EXTEND32 (GPR[RT] ^ + ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 000010,26.INSTR_INDEX:NORMAL:32::J "j <INSTR_INDEX>" *mipsI: *************** *** 1761,1767 **** --- 2040,2048 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1781,1787 **** --- 2062,2070 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1802,1808 **** --- 2085,2093 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1821,1827 **** --- 2106,2114 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1948,1954 **** --- 2235,2243 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1965,1971 **** --- 2254,2262 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1980,1985 **** --- 2271,2277 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1995,2001 **** --- 2287,2295 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2012,2017 **** --- 2306,2312 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2026,2031 **** --- 2321,2327 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2042,2048 **** --- 2338,2346 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2059,2065 **** --- 2357,2365 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2075,2081 **** --- 2375,2383 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2117,2122 **** --- 2419,2425 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2154,2160 **** --- 2457,2465 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2173,2179 **** --- 2478,2486 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2190,2196 **** --- 2497,2505 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2207,2213 **** --- 2516,2524 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2224,2230 **** --- 2535,2543 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2239,2244 **** --- 2552,2558 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2251,2257 **** --- 2565,2573 ---- 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD "madd r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2271,2277 **** --- 2587,2595 ---- 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU "maddu r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2303,2309 **** --- 2621,2629 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2329,2335 **** --- 2649,2657 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2344,2350 **** --- 2666,2674 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] != 0) *************** *** 2361,2367 **** --- 2685,2693 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] == 0) *************** *** 2376,2382 **** --- 2702,2710 ---- 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB "msub r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2396,2402 **** --- 2724,2732 ---- 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU "msubu r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2421,2427 **** --- 2751,2759 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2440,2446 **** --- 2772,2780 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2454,2460 **** --- 2788,2796 ---- 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL "mul r<RD>, r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 prod; *************** *** 2493,2499 **** --- 2829,2837 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_mult (SD_, RS, RT, 0); *************** *** 2534,2540 **** --- 2872,2880 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_multu (SD_, RS, RT, 0); *************** *** 2565,2571 **** --- 2905,2913 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2589,2595 **** --- 2931,2939 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2614,2620 **** --- 2958,2966 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2628,2634 **** --- 2974,2982 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 2645,2650 **** --- 2993,3030 ---- } + :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y + { + unsigned64 result; + + y &= 31; + TRACE_ALU_INPUT2 (x, y); + result = EXTEND32 (ROTR32 (x, y)); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR + "ror r<RD>, r<RT>, <SHIFT>" + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); + } + + 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV + "rorv r<RD>, r<RT>, r<RS>" + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); + } + + :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word { address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); *************** *** 2743,2749 **** --- 3123,3131 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2759,2765 **** --- 3141,3149 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2802,2807 **** --- 3186,3192 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2840,2845 **** --- 3225,3231 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2855,2861 **** --- 3241,3249 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2869,2874 **** --- 3257,3263 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2883,2888 **** --- 3272,3278 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2891,2896 **** --- 3281,3307 ---- } + 011111,00000,5.RT,5.RD,10000,100000::32::SEB + "seb r<RD>, r<RT>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND8 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 011111,00000,5.RT,5.RD,11000,100000::32::SEH + "seh r<RD>, r<RT>" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND16 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH "sh r<RT>, <OFFSET>(r<BASE>)" *mipsI: *************** *** 2899,2905 **** --- 3310,3318 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2939,2945 **** --- 3352,3360 ---- "ssnop":RD == 0 && RT == 0 && SHIFT == 1 "sll r<RD>, r<RT>, <SHIFT>" *mips32: + *mips32r2: *mips64: + *mips64r2: { /* Skip shift for NOP and SSNOP, so that there won't be lots of extraneous trace output. */ *************** *** 2965,2971 **** --- 3380,3388 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2989,2995 **** --- 3406,3414 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3013,3019 **** --- 3432,3440 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3037,3043 **** --- 3458,3466 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3062,3068 **** --- 3485,3493 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3089,3095 **** --- 3514,3522 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3118,3124 **** --- 3545,3553 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3146,3152 **** --- 3575,3583 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3174,3180 **** --- 3605,3613 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3191,3197 **** --- 3624,3632 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3225,3231 **** --- 3660,3668 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3242,3248 **** --- 3679,3687 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: *vr5000: *************** *** 3259,3265 **** --- 3698,3706 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3276,3282 **** --- 3717,3725 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3293,3299 **** --- 3736,3744 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3310,3316 **** --- 3755,3763 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3318,3323 **** --- 3765,3777 ---- SyncOperation (STYPE); } + 000001,5.BASE,11111,16.OFFSET::32::SYNCI + "synci <OFFSET>(r<BASE>)" + *mips32r2: + *mips64r2: + { + // sync i-cache - nothing to do currently + } 000000,20.CODE,001100:SPECIAL:32::SYSCALL "syscall %#lx<CODE>" *************** *** 3327,3333 **** --- 3781,3789 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3343,3349 **** --- 3799,3807 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3359,3365 **** --- 3817,3825 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3375,3381 **** --- 3835,3843 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3391,3397 **** --- 3853,3861 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3407,3413 **** --- 3871,3879 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3423,3429 **** --- 3889,3897 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3439,3445 **** --- 3907,3915 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3455,3461 **** --- 3925,3933 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3471,3477 **** --- 3943,3951 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3487,3493 **** --- 3961,3969 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3503,3509 **** --- 3979,3987 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3519,3525 **** --- 3997,4005 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3528,3533 **** --- 4008,4028 ---- } + 011111,00000,5.RT,5.RD,00010,100000::32::WSBH + "wsbh r<RD>, r<RT>" + *mips32r2: + *mips64r2: + { + union { unsigned32 w; unsigned16 h[2]; } u; + TRACE_ALU_INPUT1 (GPR[RT]); + u.w = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + GPR[RD] = EXTEND32 (u.w); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + :function:::void:do_xor:int rs, int rt, int rd { TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); *************** *** 3543,3549 **** --- 4038,4046 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3567,3573 **** --- 4064,4072 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3650,3655 **** --- 4149,4155 ---- *mipsIII: *mipsIV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 3663,3668 **** --- 4163,4169 ---- :function:::void:check_fmt_p:int fmt, instruction_word insn *mipsV: *mips64: + *mips64r2: { if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) *************** *** 3683,3689 **** --- 4184,4192 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3703,3708 **** --- 4206,4212 ---- :function:::unsigned64:do_load_double:address_word base, address_word offset *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3739,3744 **** --- 4243,4249 ---- :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3772,3778 **** --- 4277,4285 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3793,3799 **** --- 4300,4308 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3809,3814 **** --- 4318,4324 ---- "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>" *mipsV: *mips64: + *mips64r2: { unsigned64 fs; unsigned64 ft; *************** *** 3868,3874 **** --- 4378,4386 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: #*vr4100: *vr5000: *r3900: *************** *** 3904,3910 **** --- 4416,4424 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3923,3928 **** --- 4437,4443 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3941,3947 **** --- 4456,4464 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3989,3995 **** --- 4506,4514 ---- "cfc1 r<RT>, f<FS>" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) *************** *** 4032,4038 **** --- 4551,4559 ---- "ctc1 r<RT>, f<FS>" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); TRACE_ALU_INPUT1 (GPR[RT]); *************** *** 4053,4059 **** --- 4574,4582 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4073,4078 **** --- 4596,4602 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4090,4095 **** --- 4614,4620 ---- "cvt.ps.s f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4109,4115 **** --- 4634,4642 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4127,4132 **** --- 4654,4660 ---- "cvt.s.pl f<FD>, f<FS>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4138,4143 **** --- 4666,4672 ---- "cvt.s.pu f<FD>, f<FS>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4153,4159 **** --- 4682,4690 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4175,4181 **** --- 4706,4714 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4208,4213 **** --- 4741,4747 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4248,4253 **** --- 4782,4788 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4269,4274 **** --- 4804,4810 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4287,4293 **** --- 4823,4831 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4303,4308 **** --- 4841,4847 ---- "ldc1 f<FT>, <OFFSET>(r<BASE>)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); *************** *** 4315,4320 **** --- 4854,4860 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4329,4334 **** --- 4869,4875 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4341,4346 **** --- 4882,4888 ---- "luxc1 f<FD>, r<INDEX>(r<BASE>)" *mipsV: *mips64: + *mips64r2: { address_word base = GPR[BASE]; address_word index = GPR[INDEX]; *************** *** 4362,4368 **** --- 4904,4912 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4377,4382 **** --- 4921,4927 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4391,4396 **** --- 4936,4942 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4420,4426 **** --- 4966,4974 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4430,4435 **** --- 4978,5004 ---- TRACE_ALU_RESULT (GPR[RT]); } + 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 + "mfhc1 r<RT>, f<FS>" + *mips32r2: + *mips64r2: + { + check_fpu (SD_); + if (SizeFGR() == 64) + GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); + else if ((FS & 0x1) == 0) + GPR[RT] = EXTEND32 (FGR[FS + 1]); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", + (long) CIA); + GPR[RT] = EXTEND32 (0xBADF00D); + } + TRACE_ALU_RESULT (GPR[RT]); + } + 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt "mov.%s<FMT> f<FD>, f<FS>" *************** *** 4439,4445 **** --- 5008,5016 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4458,4464 **** --- 5029,5037 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4474,4480 **** --- 5047,5055 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4503,4509 **** --- 5078,5086 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4526,4532 **** --- 5103,5111 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4542,4547 **** --- 5121,5127 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4572,4578 **** --- 5152,5160 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4581,4586 **** --- 5163,5189 ---- StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); } + 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 + "mthc1 r<RT>, f<FS>" + *mips32r2: + *mips64r2: + { + check_fpu (SD_); + if (SizeFGR() == 64) + StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); + else if ((FS & 0x1) == 0) + StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", + (long) CIA); + StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); + } + TRACE_FP_RESULT (GPR[RT]); + } + 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt "mul.%s<FMT> f<FD>, f<FS>, f<FT>" *************** *** 4590,4596 **** --- 5193,5201 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4610,4616 **** --- 5215,5223 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4627,4632 **** --- 5234,5240 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4643,4648 **** --- 5251,5257 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4658,4663 **** --- 5267,5273 ---- "pll.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4670,4675 **** --- 5280,5286 ---- "plu.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4683,4688 **** --- 5294,5300 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 4701,4706 **** --- 5313,5319 ---- "pul.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4713,4718 **** --- 5326,5332 ---- "puu.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4726,4731 **** --- 5340,5346 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4740,4745 **** --- 5355,5361 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4758,4764 **** --- 5374,5382 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4775,4780 **** --- 5393,5399 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4787,4792 **** --- 5406,5412 ---- "sdc1 f<FT>, <OFFSET>(r<BASE>)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); *************** *** 4799,4804 **** --- 5419,5425 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4813,4818 **** --- 5434,5440 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4825,4830 **** --- 5447,5453 ---- "suxc1 f<FS>, r<INDEX>(r<BASE>)" *mipsV: *mips64: + *mips64r2: { unsigned64 v; address_word base = GPR[BASE]; *************** *** 4846,4852 **** --- 5469,5477 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4865,4871 **** --- 5490,5498 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4886,4892 **** --- 5513,5521 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4927,4932 **** --- 5556,5562 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { *************** *** 4968,4973 **** --- 5598,5604 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4986,4992 **** --- 5617,5625 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5013,5019 **** --- 5646,5654 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5034,5040 **** --- 5669,5677 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5047,5053 **** --- 5684,5692 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *************** *** 5059,5065 **** --- 5698,5706 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5070,5076 **** --- 5711,5719 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5093,5098 **** --- 5736,5742 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5105,5110 **** --- 5749,5755 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5117,5123 **** --- 5762,5770 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 5144,5150 **** --- 5791,5799 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5162,5168 **** --- 5811,5819 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5194,5200 **** --- 5845,5853 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: { *************** *** 5211,5217 **** --- 5864,5872 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5224,5230 **** --- 5879,5887 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5237,5243 **** --- 5894,5902 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5250,5256 **** --- 5909,5917 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: Index: vr.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/vr.igen,v retrieving revision 1.3 diff -c -p -r1.3 vr.igen *** vr.igen 16 Apr 2003 00:52:08 -0000 1.3 --- vr.igen 9 Nov 2004 15:49:52 -0000 *************** *** 100,134 **** GPR[rd] = store_hi_p ? HI : LO; } - // 32-bit rotate right of X by Y bits. - :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 31; - TRACE_ALU_INPUT2 (x, y); - result = EXTEND32 (ROTR32 (x, y)); - TRACE_ALU_RESULT (result); - return result; - } - - // Likewise 64-bit - :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 63; - TRACE_ALU_INPUT2 (x, y); - result = ROTR64 (x, y); - TRACE_ALU_RESULT (result); - return result; - } - - // VR4100 instructions. 000000,5.RS,5.RT,00000,00000,101000::32::MADD16 --- 100,105 ---- *************** *** 246,290 **** 0 /* single */); } - 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR - "ror r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); - } - - 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV - "rorv r<RD>, r<RT>, r<RS>" - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR - "dror r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 - "dror32 r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); - } - - 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV - "drorv r<RD>, r<RT>, r<RS>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); - } 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1 "luxc1 f<FD>, r<INDEX>(r<BASE>)" --- 217,222 ---- ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-08 18:06 ` David Ung 2004-11-09 15:54 ` David Ung @ 2004-11-09 16:12 ` Andrew Cagney 2004-11-09 16:23 ` cgd 1 sibling, 1 reply; 21+ messages in thread From: Andrew Cagney @ 2004-11-09 16:12 UTC (permalink / raw) To: David Ung; +Cc: cgd, gdb-patches, nigel David Ung wrote: > On Mon, 2004-11-08 at 16:43, Andrew Cagney wrote: > >>cgd@broadcom.com wrote: >> >>>At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: >>> >>> >>>>I shall update mips.igen with the new r2 instructions and then submit it >>>>as a patch. >>> >>> >>>cool, thanks. >> >>Don't. These new changes go in a new file, and that file gets a very >>clear FSF copyright. >> >>Andrew David, this isn't a technical decision (if it were, Chris would be right). The new changes, or more exactly the new instructions, go in a new file clearly marked (C) FSF (and for that matter clearly stating that it was contributed by MIPS Inc). As for the mark-up of the existing instructions, that's mindnumming tedium. Sorry about this pedentary. I'm off to pester another lawyer. Andrew > arhh. Chris's argument of that the rest of the tools consider rev 2 > instructions as an ISA is quite a valid one. And for consistency with > the existing structure, it looks to be the right thing to do. > But when I got to merging in the r2 instructions into mips.igen, I do > see that for every mips32 / 64 instruction, I now have to also tag them > mips32r2 / 64r2. It would probably be nicer to just tell it to include > all the mips32 instructions (which would be like treating it as an > ASE). > But then again it brings us back to the original argument, and I > probably would lean slightly towards the ISA model and be part of > mips.igen depite polluting the whole file with *mips32r2: and *mips64r2: > tags. > > David. > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-09 16:12 ` Andrew Cagney @ 2004-11-09 16:23 ` cgd 2004-11-09 17:00 ` Andrew Cagney 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2004-11-09 16:23 UTC (permalink / raw) To: Andrew Cagney; +Cc: David Ung, gdb-patches, nigel At Tue, 09 Nov 2004 11:10:40 -0500, Andrew Cagney wrote: > David, this isn't a technical decision (if it were, Chris would be > right). The new changes, or more exactly the new instructions, go in > a new file clearly marked (C) FSF (and for that matter clearly stating > that it was contributed by MIPS Inc). As for the mark-up of the > existing instructions, that's mindnumming tedium. > > Sorry about this pedentary. I'm off to pester another lawyer. Andrew, Once the legal issues are resolved on your end, will be it be acceptable from your POV to merge them all into mips.igen? Or do you believe they should always be separate? (Why is this necessary now, when it wasn't necessary back when we contributed the original mips32/mips64 support?) chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-09 16:23 ` cgd @ 2004-11-09 17:00 ` Andrew Cagney 2004-11-09 17:38 ` cgd 2004-11-09 23:36 ` Nigel Stephens 0 siblings, 2 replies; 21+ messages in thread From: Andrew Cagney @ 2004-11-09 17:00 UTC (permalink / raw) To: cgd; +Cc: David Ung, gdb-patches, nigel cgd@broadcom.com wrote: > At Tue, 09 Nov 2004 11:10:40 -0500, Andrew Cagney wrote: > >>David, this isn't a technical decision (if it were, Chris would be >>right). The new changes, or more exactly the new instructions, go in >>a new file clearly marked (C) FSF (and for that matter clearly stating >>that it was contributed by MIPS Inc). As for the mark-up of the >>existing instructions, that's mindnumming tedium. >> >>Sorry about this pedentary. I'm off to pester another lawyer. > > > Andrew, > > Once the legal issues are resolved on your end, will be it be > acceptable from your POV to merge them all into mips.igen? > > Or do you believe they should always be separate? That's a technical question, as I shouldn't, I don't care! > (Why is this necessary now, when it wasn't necessary back when we > contributed the original mips32/mips64 support?) That was a screw-up on my part. You'll see I more recently integrated the altivec instructions into the PPC as a separate file. Andrew ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-09 17:00 ` Andrew Cagney @ 2004-11-09 17:38 ` cgd 2004-11-24 17:08 ` David Ung 2004-11-09 23:36 ` Nigel Stephens 1 sibling, 1 reply; 21+ messages in thread From: cgd @ 2004-11-09 17:38 UTC (permalink / raw) To: Andrew Cagney; +Cc: David Ung, gdb-patches, nigel At Tue, 09 Nov 2004 11:59:28 -0500, Andrew Cagney wrote: > > Once the legal issues are resolved on your end, will be it be > > acceptable from your POV to merge them all into mips.igen? > > Or do you believe they should always be separate? > > That's a technical question, as I shouldn't, I don't care! actually, i didn't ask that as a technical question. it's a question about the state of the expected copyright/license on mips.igen once the any current issues are resolved. from your response, it sounds like you think that merging everything together would be not-disallowed-by-you. so, mips folks, i think the only solution for now is: (1) mark everything mips32/mips64 in mips.igen with additional mips32r2/mips64r2 markers, but (2) keep the new instructions in a separate file, which i can merge later. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-09 17:38 ` cgd @ 2004-11-24 17:08 ` David Ung 2004-11-24 18:17 ` cgd 0 siblings, 1 reply; 21+ messages in thread From: David Ung @ 2004-11-24 17:08 UTC (permalink / raw) To: cgd; +Cc: Andrew Cagney, gdb-patches, nigel [-- Attachment #1: Type: text/plain, Size: 42568 bytes --] On Tue, 2004-11-09 at 17:37, cgd@broadcom.com wrote: > At Tue, 09 Nov 2004 11:59:28 -0500, Andrew Cagney wrote: > > > Once the legal issues are resolved on your end, will be it be > > > acceptable from your POV to merge them all into mips.igen? > > > Or do you believe they should always be separate? > > > > That's a technical question, as I shouldn't, I don't care! > > actually, i didn't ask that as a technical question. it's a question > about the state of the expected copyright/license on mips.igen once > the any current issues are resolved. > > from your response, it sounds like you think that merging everything > together would be not-disallowed-by-you. > > > so, mips folks, i think the only solution for now is: > > (1) mark everything mips32/mips64 in mips.igen with additional > mips32r2/mips64r2 markers, but > > (2) keep the new instructions in a separate file, which i can merge > later. > > > > chris ok.. here we go again.. :) whenever you are ready Andrew. David Index: ChangeLog =================================================================== RCS file: /cvs/uberbaum/sim/mips/ChangeLog,v retrieving revision 1.109 diff -c -p -r1.109 ChangeLog *** ChangeLog 24 Sep 2004 20:28:24 -0000 1.109 --- ChangeLog 24 Nov 2004 17:02:01 -0000 *************** *** 1,3 **** --- 1,18 ---- + 2004-11-24 David Ung <davidu@mips.com> + + * mips.igen: Added models mips32r2 and mips64r2. Tag all existing + instructions which are applicable to mips32r2/mips64r2. + + * mips3264r2.igen: New file for mips 32/64 revision 2 specific + instructions. + + * vr.igen: The following instructions: ror, rorv, dror, dror32, + drorv and their corresponding worker functions do_ror/dodror are + moved into mips.igen. + + * configure.in: Add targets mipsisa32r2*-*-* and mipsisa64r2*-*-* + to use mips32r2/64r2 models. + 2004-09-24 Monika Chaddha <monika@acmet.com> Committed by Andrew Cagney. Index: configure.in =================================================================== RCS file: /cvs/uberbaum/sim/mips/configure.in,v retrieving revision 1.8 diff -c -p -r1.8 configure.in *** configure.in 19 Aug 2004 07:02:04 -0000 1.8 --- configure.in 24 Nov 2004 17:02:01 -0000 *************** case "${target}" in *** 141,146 **** --- 141,151 ---- sim_igen_filter="32,64,f" sim_m16_filter="16" ;; + mipsisa32r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips32r2" + sim_igen_filter="32,f" + sim_mach_default="mipsisa32r2" + ;; mipsisa32*-*-*) sim_gen=IGEN sim_igen_machine="-M mips32" sim_igen_filter="32,f" *************** case "${target}" in *** 151,156 **** --- 156,166 ---- sim_igen_filter="32,64,f" sim_mach_default="mips_sb1" ;; + mipsisa64r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips64r2,mips3d" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64r2" + ;; mipsisa64*-*-*) sim_gen=IGEN sim_igen_machine="-M mips64,mips3d" sim_igen_filter="32,64,f" Index: mips.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/mips.igen,v retrieving revision 1.57 diff -c -p -r1.57 mips.igen *** mips.igen 10 Apr 2004 06:51:49 -0000 1.57 --- mips.igen 24 Nov 2004 17:02:01 -0000 *************** *** 45,51 **** --- 45,53 ---- :model:::mipsIV:mips8000: :model:::mipsV:mipsisaV: :model:::mips32:mipsisa32: + :model:::mips32r2:mipsisa32r2: :model:::mips64:mipsisa64: + :model:::mips64r2:mipsisa64r2: // Vendor ISAs: // *************** *** 132,137 **** --- 134,140 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 141,146 **** --- 144,150 ---- :function:::address_word:loadstore_ea:address_word base, address_word offset *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ /* If in user mode and UX is not set, use 32-bit compatibility effective *************** *** 178,183 **** --- 182,188 ---- :function:::int:not_word_value:unsigned_word value *mips32: + *mips32r2: { /* On MIPS32, since registers are 32-bits, there's no check to be done. */ return 0; *************** *** 185,190 **** --- 190,196 ---- :function:::int:not_word_value:unsigned_word value *mips64: + *mips64r2: { return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); } *************** *** 212,218 **** --- 218,226 ---- :function:::void:unpredictable: *mips32: + *mips32r2: *mips64: + *mips64r2: { unpredictable_action (CPU, CIA); } *************** *** 300,306 **** --- 308,316 ---- :function:::int:check_mt_hilo:hilo_history *history *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { signed64 time = sim_events_time (SD); *************** *** 322,328 **** --- 332,340 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 392,398 **** --- 404,412 ---- :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { /* FIXME: could record the fact that a stall occured if we want */ *************** *** 445,451 **** --- 459,467 ---- :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: { signed64 time = sim_events_time (SD); hi->op.timestamp = time; *************** *** 468,479 **** --- 484,498 ---- *mipsV: *vr4100: *vr5000: + *vr5400: + *vr5500: { // The check should be similar to mips64 for any with PX/UX bit equivalents. } :function:::void:check_u64:instruction_word insn *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ if (UserMode && (SR & (status_UX|status_PX)) == 0) *************** *** 486,492 **** // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32, mips64) // --- 505,511 ---- // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) // *************** *** 499,505 **** --- 518,526 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 525,531 **** --- 546,554 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 560,566 **** --- 583,591 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 587,593 **** --- 612,620 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 612,618 **** --- 639,647 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 630,636 **** --- 659,667 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 650,656 **** --- 681,689 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 671,677 **** --- 704,712 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 695,701 **** --- 730,738 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 717,723 **** --- 754,762 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 741,747 **** --- 780,788 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 769,775 **** --- 810,818 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 793,799 **** --- 836,844 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 814,820 **** --- 859,867 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 840,846 **** --- 887,895 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 863,869 **** --- 912,920 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 887,893 **** --- 938,946 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 909,915 **** --- 962,970 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 935,941 **** --- 990,998 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 961,967 **** --- 1018,1026 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 987,993 **** --- 1046,1054 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1008,1014 **** --- 1069,1077 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1032,1038 **** --- 1095,1103 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1068,1074 **** --- 1133,1141 ---- 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO "clo r<RD>, r<RS>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1093,1099 **** --- 1160,1168 ---- 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ "clz r<RD>, r<RS>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1121,1126 **** --- 1190,1196 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1142,1147 **** --- 1212,1218 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1170,1175 **** --- 1241,1247 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1192,1197 **** --- 1264,1270 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1204,1209 **** --- 1277,1283 ---- 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO "dclo r<RD>, r<RS>" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1228,1233 **** --- 1302,1308 ---- 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ "dclz r<RD>, r<RS>" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1285,1290 **** --- 1360,1366 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1325,1330 **** --- 1401,1407 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1332,1339 **** do_ddivu (SD_, RS, RT); } - - :function:::void:do_div:int rs, int rt { check_div_hilo (SD_, HIHISTORY, LOHISTORY); --- 1409,1414 ---- *************** *** 1368,1374 **** --- 1443,1451 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1407,1413 **** --- 1484,1492 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1416,1422 **** } - :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p { unsigned64 lo; --- 1495,1500 ---- *************** *** 1488,1493 **** --- 1566,1572 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1516,1521 **** --- 1595,1601 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1531,1536 **** --- 1611,1659 ---- do_dmultu (SD_, RS, RT, RD); } + + :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y + { + unsigned64 result; + + y &= 63; + TRACE_ALU_INPUT2 (x, y); + result = ROTR64 (x, y); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR + "dror r<RD>, r<RT>, <SHIFT>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 + "dror32 r<RD>, r<RT>, <SHIFT>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); + } + + 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV + "drorv r<RD>, r<RT>, r<RS>" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); + } + + :function:::void:do_dsll:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); *************** *** 1544,1549 **** --- 1667,1673 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1558,1563 **** --- 1682,1688 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1582,1587 **** --- 1707,1713 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1603,1608 **** --- 1729,1735 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1617,1622 **** --- 1744,1750 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1642,1647 **** --- 1770,1776 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1663,1668 **** --- 1792,1798 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1677,1682 **** --- 1807,1813 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1704,1709 **** --- 1835,1841 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1718,1723 **** --- 1850,1856 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1745,1750 **** --- 1878,1884 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1761,1767 **** --- 1895,1903 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1781,1787 **** --- 1917,1925 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1802,1808 **** --- 1940,1948 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1821,1827 **** --- 1961,1969 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1948,1954 **** --- 2090,2098 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1965,1971 **** --- 2109,2117 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1980,1985 **** --- 2126,2132 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1995,2001 **** --- 2142,2150 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2012,2017 **** --- 2161,2167 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2026,2031 **** --- 2176,2182 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2042,2048 **** --- 2193,2201 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2059,2065 **** --- 2212,2220 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2075,2081 **** --- 2230,2238 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2117,2122 **** --- 2274,2280 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2154,2160 **** --- 2312,2320 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2173,2179 **** --- 2333,2341 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2190,2196 **** --- 2352,2360 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2207,2213 **** --- 2371,2379 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2224,2230 **** --- 2390,2398 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2239,2244 **** --- 2407,2413 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2251,2257 **** --- 2420,2428 ---- 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD "madd r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2271,2277 **** --- 2442,2450 ---- 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU "maddu r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2303,2309 **** --- 2476,2484 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2329,2335 **** --- 2504,2512 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2344,2350 **** --- 2521,2529 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] != 0) *************** *** 2361,2367 **** --- 2540,2548 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] == 0) *************** *** 2376,2382 **** --- 2557,2565 ---- 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB "msub r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2396,2402 **** --- 2579,2587 ---- 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU "msubu r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2421,2427 **** --- 2606,2614 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2440,2446 **** --- 2627,2635 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2454,2460 **** --- 2643,2651 ---- 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL "mul r<RD>, r<RS>, r<RT>" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 prod; *************** *** 2493,2499 **** --- 2684,2692 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_mult (SD_, RS, RT, 0); *************** *** 2534,2540 **** --- 2727,2735 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_multu (SD_, RS, RT, 0); *************** *** 2565,2571 **** --- 2760,2768 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2589,2595 **** --- 2786,2794 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2614,2620 **** --- 2813,2821 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2628,2634 **** --- 2829,2837 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 2645,2650 **** --- 2848,2885 ---- } + :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y + { + unsigned64 result; + + y &= 31; + TRACE_ALU_INPUT2 (x, y); + result = EXTEND32 (ROTR32 (x, y)); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR + "ror r<RD>, r<RT>, <SHIFT>" + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); + } + + 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV + "rorv r<RD>, r<RT>, r<RS>" + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); + } + + :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word { address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); *************** *** 2743,2749 **** --- 2978,2986 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2759,2765 **** --- 2996,3004 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2802,2807 **** --- 3041,3047 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2840,2845 **** --- 3080,3086 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2855,2861 **** --- 3096,3104 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2869,2874 **** --- 3112,3118 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2883,2888 **** --- 3127,3133 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2891,2896 **** --- 3136,3142 ---- } + 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH "sh r<RT>, <OFFSET>(r<BASE>)" *mipsI: *************** *** 2899,2905 **** --- 3145,3153 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2939,2945 **** --- 3187,3195 ---- "ssnop":RD == 0 && RT == 0 && SHIFT == 1 "sll r<RD>, r<RT>, <SHIFT>" *mips32: + *mips32r2: *mips64: + *mips64r2: { /* Skip shift for NOP and SSNOP, so that there won't be lots of extraneous trace output. */ *************** *** 2965,2971 **** --- 3215,3223 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2989,2995 **** --- 3241,3249 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3013,3019 **** --- 3267,3275 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3037,3043 **** --- 3293,3301 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3062,3068 **** --- 3320,3328 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3089,3095 **** --- 3349,3357 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3118,3124 **** --- 3380,3388 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3146,3152 **** --- 3410,3418 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3174,3180 **** --- 3440,3448 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3191,3197 **** --- 3459,3467 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3225,3231 **** --- 3495,3503 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3242,3248 **** --- 3514,3522 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: *vr5000: *************** *** 3259,3265 **** --- 3533,3541 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3276,3282 **** --- 3552,3560 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3293,3299 **** --- 3571,3579 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3310,3316 **** --- 3590,3598 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3327,3333 **** --- 3609,3617 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3343,3349 **** --- 3627,3635 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3359,3365 **** --- 3645,3653 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3375,3381 **** --- 3663,3671 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3391,3397 **** --- 3681,3689 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3407,3413 **** --- 3699,3707 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3423,3429 **** --- 3717,3725 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3439,3445 **** --- 3735,3743 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3455,3461 **** --- 3753,3761 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3471,3477 **** --- 3771,3779 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3487,3493 **** --- 3789,3797 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3503,3509 **** --- 3807,3815 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3519,3525 **** --- 3825,3833 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3543,3549 **** --- 3851,3859 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3567,3573 **** --- 3877,3885 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3650,3655 **** --- 3962,3968 ---- *mipsIII: *mipsIV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 3663,3668 **** --- 3976,3982 ---- :function:::void:check_fmt_p:int fmt, instruction_word insn *mipsV: *mips64: + *mips64r2: { if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) *************** *** 3683,3689 **** --- 3997,4005 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3703,3708 **** --- 4019,4025 ---- :function:::unsigned64:do_load_double:address_word base, address_word offset *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3739,3744 **** --- 4056,4062 ---- :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3772,3778 **** --- 4090,4098 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3793,3799 **** --- 4113,4121 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3809,3814 **** --- 4131,4137 ---- "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>" *mipsV: *mips64: + *mips64r2: { unsigned64 fs; unsigned64 ft; *************** *** 3868,3874 **** --- 4191,4199 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: #*vr4100: *vr5000: *r3900: *************** *** 3904,3910 **** --- 4229,4237 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3923,3928 **** --- 4250,4256 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3941,3947 **** --- 4269,4277 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3989,3995 **** --- 4319,4327 ---- "cfc1 r<RT>, f<FS>" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) *************** *** 4032,4038 **** --- 4364,4372 ---- "ctc1 r<RT>, f<FS>" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); TRACE_ALU_INPUT1 (GPR[RT]); *************** *** 4053,4059 **** --- 4387,4395 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4073,4078 **** --- 4409,4415 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4090,4095 **** --- 4427,4433 ---- "cvt.ps.s f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4109,4115 **** --- 4447,4455 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4127,4132 **** --- 4467,4473 ---- "cvt.s.pl f<FD>, f<FS>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4138,4143 **** --- 4479,4485 ---- "cvt.s.pu f<FD>, f<FS>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4153,4159 **** --- 4495,4503 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4175,4181 **** --- 4519,4527 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4208,4213 **** --- 4554,4560 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4248,4253 **** --- 4595,4601 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4269,4274 **** --- 4617,4623 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4287,4293 **** --- 4636,4644 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4303,4308 **** --- 4654,4660 ---- "ldc1 f<FT>, <OFFSET>(r<BASE>)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); *************** *** 4315,4320 **** --- 4667,4673 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4329,4334 **** --- 4682,4688 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4341,4346 **** --- 4695,4701 ---- "luxc1 f<FD>, r<INDEX>(r<BASE>)" *mipsV: *mips64: + *mips64r2: { address_word base = GPR[BASE]; address_word index = GPR[INDEX]; *************** *** 4362,4368 **** --- 4717,4725 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4377,4382 **** --- 4734,4740 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4391,4396 **** --- 4749,4755 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4420,4426 **** --- 4779,4787 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4439,4445 **** --- 4800,4808 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4458,4464 **** --- 4821,4829 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4474,4480 **** --- 4839,4847 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4503,4509 **** --- 4870,4878 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4526,4532 **** --- 4895,4903 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4542,4547 **** --- 4913,4919 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4572,4578 **** --- 4944,4952 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4590,4596 **** --- 4964,4972 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4610,4616 **** --- 4986,4994 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4627,4632 **** --- 5005,5011 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4643,4648 **** --- 5022,5028 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4658,4663 **** --- 5038,5044 ---- "pll.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4670,4675 **** --- 5051,5057 ---- "plu.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4683,4688 **** --- 5065,5071 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 4701,4706 **** --- 5084,5090 ---- "pul.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4713,4718 **** --- 5097,5103 ---- "puu.ps f<FD>, f<FS>, f<FT>" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4726,4731 **** --- 5111,5117 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4740,4745 **** --- 5126,5132 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4758,4764 **** --- 5145,5153 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4775,4780 **** --- 5164,5170 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4787,4792 **** --- 5177,5183 ---- "sdc1 f<FT>, <OFFSET>(r<BASE>)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); *************** *** 4799,4804 **** --- 5190,5196 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4813,4818 **** --- 5205,5211 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4825,4830 **** --- 5218,5224 ---- "suxc1 f<FS>, r<INDEX>(r<BASE>)" *mipsV: *mips64: + *mips64r2: { unsigned64 v; address_word base = GPR[BASE]; *************** *** 4846,4852 **** --- 5240,5248 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4865,4871 **** --- 5261,5269 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4886,4892 **** --- 5284,5292 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4927,4932 **** --- 5327,5333 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { *************** *** 4968,4973 **** --- 5369,5375 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4986,4992 **** --- 5388,5396 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5013,5019 **** --- 5417,5425 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5034,5040 **** --- 5440,5448 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5047,5053 **** --- 5455,5463 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *************** *** 5059,5065 **** --- 5469,5477 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5070,5076 **** --- 5482,5490 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5093,5098 **** --- 5507,5513 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5105,5110 **** --- 5520,5526 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5117,5123 **** --- 5533,5541 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 5144,5150 **** --- 5562,5570 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5162,5168 **** --- 5582,5590 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5194,5200 **** --- 5616,5624 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: { *************** *** 5211,5217 **** --- 5635,5643 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5224,5230 **** --- 5650,5658 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5237,5243 **** --- 5665,5673 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5250,5264 **** *mipsIV: *mipsV: *mips32: *mips64: *vr4100: *vr5000: ! \f :include:::m16.igen :include:::mdmx.igen :include:::mips3d.igen :include:::sb1.igen :include:::tx.igen :include:::vr.igen ! \f --- 5680,5697 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: ! ! :include:::mips3264r2.igen :include:::m16.igen :include:::mdmx.igen :include:::mips3d.igen :include:::sb1.igen :include:::tx.igen :include:::vr.igen ! Index: vr.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/vr.igen,v retrieving revision 1.3 diff -c -p -r1.3 vr.igen *** vr.igen 16 Apr 2003 00:52:08 -0000 1.3 --- vr.igen 24 Nov 2004 17:02:01 -0000 *************** *** 100,134 **** GPR[rd] = store_hi_p ? HI : LO; } - // 32-bit rotate right of X by Y bits. - :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 31; - TRACE_ALU_INPUT2 (x, y); - result = EXTEND32 (ROTR32 (x, y)); - TRACE_ALU_RESULT (result); - return result; - } - - // Likewise 64-bit - :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 63; - TRACE_ALU_INPUT2 (x, y); - result = ROTR64 (x, y); - TRACE_ALU_RESULT (result); - return result; - } - - // VR4100 instructions. 000000,5.RS,5.RT,00000,00000,101000::32::MADD16 --- 100,105 ---- *************** *** 246,290 **** 0 /* single */); } - 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR - "ror r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); - } - - 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV - "rorv r<RD>, r<RT>, r<RS>" - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR - "dror r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 - "dror32 r<RD>, r<RT>, <SHIFT>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); - } - - 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV - "drorv r<RD>, r<RT>, r<RS>" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); - } 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1 "luxc1 f<FD>, r<INDEX>(r<BASE>)" --- 217,222 ---- [-- Attachment #2: mips3264r2.igen --] [-- Type: text/plain, Size: 6173 bytes --] // -*- C -*- // Simulator definition for the MIPS 32/64 revision 2 instructions. // Copyright (C) 2004 Free Software Foundation, Inc. // Contributed by David Ung, of MIPS Technologies. // // This file is part of GDB, the GNU debugger. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License along // with this program; if not, write to the Free Software Foundation, Inc., // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT "dext r<RT>, r<RS>, <LSB>, <SIZE+1>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); TRACE_ALU_RESULT1 (GPR[RT]); } 010000,01011,5.RT,01100,00000,0,00,000::32::DI "di":RT == 0 "di r<RT>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT0 (); GPR[RT] = EXTEND32 (SR); SR &= ~status_IE; TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB + 32) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>" *mips64r2: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) & MASK64 (MSB + 32, LSB + 32); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,00000,5.RT,5.RD,00010,100100::64::DSBH "dsbh r<RD>, r<RT>" *mips64r2: { union { unsigned64 d; unsigned16 h[4]; } u; check_u64 (SD_, instruction_0); TRACE_ALU_INPUT1 (GPR[RT]); u.d = GPR[RT]; u.h[0] = SWAP_2 (u.h[0]); u.h[1] = SWAP_2 (u.h[1]); u.h[2] = SWAP_2 (u.h[2]); u.h[3] = SWAP_2 (u.h[3]); GPR[RD] = u.d; TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,00101,100100::64::DSHD "dshd r<RD>, r<RT>" *mips64r2: { unsigned64 d; check_u64 (SD_, instruction_0); TRACE_ALU_INPUT1 (GPR[RT]); d = GPR[RT]; GPR[RD] = ((d >> 48) | (d << 48) | ((d & 0x0000ffff00000000) >> 16) | ((d & 0x00000000ffff0000) << 16)); TRACE_ALU_RESULT1 (GPR[RD]); } 010000,01011,5.RT,01100,00000,1,00,000::32::EI "ei":RT == 0 "ei r<RT>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT0 (); GPR[RT] = EXTEND32 (SR); SR |= status_IE; TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT "ext r<RT>, r<RS>, <LSB>, <SIZE+1>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); TRACE_ALU_RESULT1 (GPR[RT]); } 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 "mfhc1 r<RT>, f<FS>" *mips32r2: *mips64r2: { check_fpu (SD_); if (SizeFGR() == 64) GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); else if ((FS & 0x1) == 0) GPR[RT] = EXTEND32 (FGR[FS + 1]); else { if (STATE_VERBOSE_P(SD)) sim_io_eprintf (SD, "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", (long) CIA); GPR[RT] = EXTEND32 (0xBADF00D); } TRACE_ALU_RESULT (GPR[RT]); } 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 "mthc1 r<RT>, f<FS>" *mips32r2: *mips64r2: { check_fpu (SD_); if (SizeFGR() == 64) StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); else if ((FS & 0x1) == 0) StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); else { if (STATE_VERBOSE_P(SD)) sim_io_eprintf (SD, "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", (long) CIA); StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); } TRACE_FP_RESULT (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS "ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] = EXTEND32 (GPR[RT] ^ ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,00000,5.RT,5.RD,10000,100000::32::SEB "seb r<RD>, r<RT>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT1 (GPR[RT]); GPR[RD] = EXTEND8 (GPR[RT]); TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,11000,100000::32::SEH "seh r<RD>, r<RT>" *mips32r2: *mips64r2: { TRACE_ALU_INPUT1 (GPR[RT]); GPR[RD] = EXTEND16 (GPR[RT]); TRACE_ALU_RESULT1 (GPR[RD]); } 000001,5.BASE,11111,16.OFFSET::32::SYNCI "synci <OFFSET>(r<BASE>)" *mips32r2: *mips64r2: { // sync i-cache - nothing to do currently } 011111,00000,5.RT,5.RD,00010,100000::32::WSBH "wsbh r<RD>, r<RT>" *mips32r2: *mips64r2: { union { unsigned32 w; unsigned16 h[2]; } u; TRACE_ALU_INPUT1 (GPR[RT]); u.w = GPR[RT]; u.h[0] = SWAP_2 (u.h[0]); u.h[1] = SWAP_2 (u.h[1]); GPR[RD] = EXTEND32 (u.w); TRACE_ALU_RESULT1 (GPR[RD]); } ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-24 17:08 ` David Ung @ 2004-11-24 18:17 ` cgd 2005-05-18 18:11 ` [patch ping] " David Ung 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2004-11-24 18:17 UTC (permalink / raw) To: David Ung; +Cc: Andrew Cagney, gdb-patches, nigel At Wed, 24 Nov 2004 17:07:28 +0000, David Ung wrote: > whenever you are ready Andrew. Actually, it's for me to approve, now that Andrew's general objection is resolved. I'll try to review the changes ASAP. (I've been feeling guilty about not having time to actually review the last rev.) Thanks for your patience. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* [patch ping] MIPS32 / MIPS64 release 2 support in simulator 2004-11-24 18:17 ` cgd @ 2005-05-18 18:11 ` David Ung 2005-05-19 2:04 ` cgd 0 siblings, 1 reply; 21+ messages in thread From: David Ung @ 2005-05-18 18:11 UTC (permalink / raw) To: cgd; +Cc: gdb-patches Towards the end of last year, I submit a patch for MIPS32 / MIPS64 release 2 support in the GNU simulator. I am planning to add support in GCC, and I think it would be a good idea to have it in the simulator too. I know its been 6 months, so thought I should chase it up? :) David. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch ping] MIPS32 / MIPS64 release 2 support in simulator 2005-05-18 18:11 ` [patch ping] " David Ung @ 2005-05-19 2:04 ` cgd [not found] ` <mailpost.1116450142.2303@news-sj1-1> 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2005-05-19 2:04 UTC (permalink / raw) To: David Ung; +Cc: gdb-patches I feel **remarkably** bad about this. I've been thinking about it for a few seconds just about every day for the last few months. I will get to it ASAP, I promise. chris At Wed, 18 May 2005 17:29:23 +0100, David Ung wrote: > Towards the end of last year, I submit a patch for MIPS32 / MIPS64 > release 2 support in the GNU simulator. > I am planning to add support in GCC, and I think it would be a good idea > to have it in the simulator too. > I know its been 6 months, so thought I should chase it up? :) > > David. ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <mailpost.1116450142.2303@news-sj1-1>]
* Re: [patch ping] MIPS32 / MIPS64 release 2 support in simulator [not found] ` <mailpost.1116450142.2303@news-sj1-1> @ 2005-05-25 2:21 ` cgd 2005-05-26 22:27 ` cgd 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2005-05-25 2:21 UTC (permalink / raw) To: David Ung; +Cc: gdb-patches just so you know i haven't forgotten: I'm trying to do do a basic build + sanity check of these changes Right Now. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch ping] MIPS32 / MIPS64 release 2 support in simulator 2005-05-25 2:21 ` cgd @ 2005-05-26 22:27 ` cgd 2005-05-27 14:38 ` David Ung 0 siblings, 1 reply; 21+ messages in thread From: cgd @ 2005-05-26 22:27 UTC (permalink / raw) To: David Ung; +Cc: gdb-patches At 24 May 2005 14:31:04 -0700, Chris G. Demetriou wrote: > just so you know i haven't forgotten: I'm trying to do do a basic > build + sanity check of these changes Right Now. I've just checked them in. I reformatted your changelog a bit to be more like the normal GNU style. (I figured it'd be really, really poor form to ask you to do that. 8-) i tested them by finding a version of gcc which would builds mipsisa64-elf, and checking before and after. I.e., i checked to see that the MIPS64 code wasn't broken, but didn't check the MIPS32r4/MIPS64r2 code. I figure you'll be doing that regularly. thanks, and I apologize again for the delay. chris ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch ping] MIPS32 / MIPS64 release 2 support in simulator 2005-05-26 22:27 ` cgd @ 2005-05-27 14:38 ` David Ung 0 siblings, 0 replies; 21+ messages in thread From: David Ung @ 2005-05-27 14:38 UTC (permalink / raw) To: cgd; +Cc: gdb-patches On Thu, 2005-05-26 at 14:33 -0700, cgd@broadcom.com wrote: > At 24 May 2005 14:31:04 -0700, Chris G. Demetriou wrote: > > just so you know i haven't forgotten: I'm trying to do do a basic > > build + sanity check of these changes Right Now. > > I've just checked them in. thanks. > I reformatted your changelog a bit to be more like the normal GNU > style. (I figured it'd be really, really poor form to ask you to do > that. 8-) The less change I have to make, the better it is for me.. ;) > i tested them by finding a version of gcc which would builds > mipsisa64-elf, and checking before and after. I.e., i checked to see > that the MIPS64 code wasn't broken, but didn't check the > MIPS32r4/MIPS64r2 code. > > I figure you'll be doing that regularly. yes. We ran mips32r2 checks regularly but not mips64r2. We do check mips64 though. David. ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: MIPS32 / MIPS64 release 2 support in simulator 2004-11-09 17:00 ` Andrew Cagney 2004-11-09 17:38 ` cgd @ 2004-11-09 23:36 ` Nigel Stephens 1 sibling, 0 replies; 21+ messages in thread From: Nigel Stephens @ 2004-11-09 23:36 UTC (permalink / raw) To: Andrew Cagney; +Cc: cgd, David Ung, gdb-patches Andrew Cagney wrote: > That was a screw-up on my part. You'll see I more recently integrated > the altivec instructions into the PPC as a separate file. > Hi Andrew I'm not sure that I understand what the problem is. Can we help to sort out the legal issues by sending a letter or email from an officer of MIPS Technologies stating our intentions more clearly? We want to make sure that we can contribute further patches to GDB and the simulator without undue hassle. Regards Nigel ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2005-05-27 10:34 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2004-11-03 15:26 MIPS32 / MIPS64 release 2 support in simulator David Ung
[not found] ` <mailpost.1099495587.2562@news-sj1-1>
2004-11-03 16:54 ` cgd
2004-11-03 16:57 ` cgd
[not found] ` <mailpost.1099501062.5136@news-sj1-1>
2004-11-03 19:01 ` cgd
2004-11-04 13:53 ` David Ung
[not found] ` <mailpost.1099576418.9773@news-sj1-1>
2004-11-04 17:46 ` cgd
2004-11-08 16:44 ` Andrew Cagney
2004-11-08 18:06 ` David Ung
2004-11-09 15:54 ` David Ung
2004-11-09 16:12 ` Andrew Cagney
2004-11-09 16:23 ` cgd
2004-11-09 17:00 ` Andrew Cagney
2004-11-09 17:38 ` cgd
2004-11-24 17:08 ` David Ung
2004-11-24 18:17 ` cgd
2005-05-18 18:11 ` [patch ping] " David Ung
2005-05-19 2:04 ` cgd
[not found] ` <mailpost.1116450142.2303@news-sj1-1>
2005-05-25 2:21 ` cgd
2005-05-26 22:27 ` cgd
2005-05-27 14:38 ` David Ung
2004-11-09 23:36 ` Nigel Stephens
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox