From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9314 invoked by alias); 9 Nov 2004 15:54:27 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 8835 invoked from network); 9 Nov 2004 15:53:33 -0000 Received: from unknown (HELO dmz.algor.co.uk) (62.254.210.145) by sourceware.org with SMTP; 9 Nov 2004 15:53:33 -0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CRYRQ-00057k-00; Tue, 09 Nov 2004 16:01:56 +0000 Received: from stockwell.mips.com ([192.168.192.238]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CRYJ3-0003Bb-00; Tue, 09 Nov 2004 15:53:17 +0000 Subject: Re: MIPS32 / MIPS64 release 2 support in simulator From: David Ung To: Andrew Cagney Cc: cgd@broadcom.com, gdb-patches@sources.redhat.com, nigel@mips.com In-Reply-To: <1099937194.2780.151.camel@stockwell.mips.com> References: <1099495559.2778.53.camel@stockwell.mips.com> <1099576389.2778.90.camel@stockwell.mips.com> <418FA243.4060507@gnu.org> <1099937194.2780.151.camel@stockwell.mips.com> Content-Type: text/plain Organization: MIPS Technologies UK Message-Id: <1100015596.12540.13.camel@stockwell.mips.com> Mime-Version: 1.0 Date: Tue, 09 Nov 2004 15:54:00 -0000 Content-Transfer-Encoding: 7bit X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-3.284, required 4, AWL, BAYES_00, HTML_MESSAGE, SPAMMYSPELL) X-SW-Source: 2004-11/txt/msg00161.txt.bz2 On Mon, 2004-11-08 at 18:06, David Ung wrote: > On Mon, 2004-11-08 at 16:43, Andrew Cagney wrote: > > cgd@broadcom.com wrote: > > > At Thu, 4 Nov 2004 13:53:38 +0000 (UTC), "David Ung" wrote: > > > > > >>I shall update mips.igen with the new r2 instructions and then submit it > > >>as a patch. > > > > > > > > > cool, thanks. > > > > Don't. These new changes go in a new file, and that file gets a very > > clear FSF copyright. > > > > Andrew > > > > arhh. Chris's argument of that the rest of the tools consider rev 2 > instructions as an ISA is quite a valid one. And for consistency with > the existing structure, it looks to be the right thing to do. > But when I got to merging in the r2 instructions into mips.igen, I do > see that for every mips32 / 64 instruction, I now have to also tag them > mips32r2 / 64r2. It would probably be nicer to just tell it to include > all the mips32 instructions (which would be like treating it as an > ASE). > But then again it brings us back to the original argument, and I > probably would lean slightly towards the ISA model and be part of > mips.igen depite polluting the whole file with *mips32r2: and *mips64r2: > tags. > > David. > For now, I am assuming we are going for the all in one mips.igen approach. So here is the new patch for release 2 instructions. David. Index: ChangeLog =================================================================== RCS file: /cvs/uberbaum/sim/mips/ChangeLog,v retrieving revision 1.109 diff -c -p -r1.109 ChangeLog *** ChangeLog 24 Sep 2004 20:28:24 -0000 1.109 --- ChangeLog 9 Nov 2004 15:49:51 -0000 *************** *** 1,3 **** --- 1,16 ---- + 2004-11-09 David Ung + + * mips.igen (mips64r2:): Added models mips32r2 and mips64r2. Tag + all existing instructions which are applicable to + mips32r2/mips64r2, and add new release 2 instructions. + + * vr.igen: The following instructions: ror, rorv, dror, dror32, + drorv and their corresponding worker functions do_ror/dodror are + moved into mips.igen. + + * configure.in: Add targets mipsisa32r2*-*-* and mipsisa64r2*-*-* + to use mips32r2/64r2 models. + 2004-09-24 Monika Chaddha Committed by Andrew Cagney. Index: configure.in =================================================================== RCS file: /cvs/uberbaum/sim/mips/configure.in,v retrieving revision 1.8 diff -c -p -r1.8 configure.in *** configure.in 19 Aug 2004 07:02:04 -0000 1.8 --- configure.in 9 Nov 2004 15:49:51 -0000 *************** case "${target}" in *** 141,146 **** --- 141,151 ---- sim_igen_filter="32,64,f" sim_m16_filter="16" ;; + mipsisa32r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips32r2" + sim_igen_filter="32,f" + sim_mach_default="mipsisa32r2" + ;; mipsisa32*-*-*) sim_gen=IGEN sim_igen_machine="-M mips32" sim_igen_filter="32,f" *************** case "${target}" in *** 151,156 **** --- 156,166 ---- sim_igen_filter="32,64,f" sim_mach_default="mips_sb1" ;; + mipsisa64r2*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips64r2,mips3d" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64r2" + ;; mipsisa64*-*-*) sim_gen=IGEN sim_igen_machine="-M mips64,mips3d" sim_igen_filter="32,64,f" Index: mips.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/mips.igen,v retrieving revision 1.57 diff -c -p -r1.57 mips.igen *** mips.igen 10 Apr 2004 06:51:49 -0000 1.57 --- mips.igen 9 Nov 2004 15:49:52 -0000 *************** *** 45,51 **** --- 45,53 ---- :model:::mipsIV:mips8000: :model:::mipsV:mipsisaV: :model:::mips32:mipsisa32: + :model:::mips32r2:mipsisa32r2: :model:::mips64:mipsisa64: + :model:::mips64r2:mipsisa64r2: // Vendor ISAs: // *************** *** 132,137 **** --- 134,140 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 141,146 **** --- 144,150 ---- :function:::address_word:loadstore_ea:address_word base, address_word offset *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ /* If in user mode and UX is not set, use 32-bit compatibility effective *************** *** 178,183 **** --- 182,188 ---- :function:::int:not_word_value:unsigned_word value *mips32: + *mips32r2: { /* On MIPS32, since registers are 32-bits, there's no check to be done. */ return 0; *************** *** 185,190 **** --- 190,196 ---- :function:::int:not_word_value:unsigned_word value *mips64: + *mips64r2: { return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); } *************** *** 212,218 **** --- 218,226 ---- :function:::void:unpredictable: *mips32: + *mips32r2: *mips64: + *mips64r2: { unpredictable_action (CPU, CIA); } *************** *** 300,306 **** --- 308,316 ---- :function:::int:check_mt_hilo:hilo_history *history *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { signed64 time = sim_events_time (SD); *************** *** 322,328 **** --- 332,340 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 392,398 **** --- 404,412 ---- :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: *r3900: { /* FIXME: could record the fact that a stall occured if we want */ *************** *** 445,451 **** --- 459,467 ---- :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo *mips32: + *mips32r2: *mips64: + *mips64r2: { signed64 time = sim_events_time (SD); hi->op.timestamp = time; *************** *** 468,479 **** --- 484,498 ---- *mipsV: *vr4100: *vr5000: + *vr5400: + *vr5500: { // The check should be similar to mips64 for any with PX/UX bit equivalents. } :function:::void:check_u64:instruction_word insn *mips64: + *mips64r2: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ if (UserMode && (SR & (status_UX|status_PX)) == 0) *************** *** 486,492 **** // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32, mips64) // --- 505,511 ---- // // MIPS Architecture: // ! // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) // *************** *** 499,505 **** --- 518,526 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 525,531 **** --- 546,554 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 560,566 **** --- 583,591 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 587,593 **** --- 612,620 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 612,618 **** --- 639,647 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 630,636 **** --- 659,667 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 650,656 **** --- 681,689 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 671,677 **** --- 704,712 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 695,701 **** --- 730,738 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 717,723 **** --- 754,762 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 741,747 **** --- 780,788 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 769,775 **** --- 810,818 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 793,799 **** --- 836,844 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 814,820 **** --- 859,867 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 840,846 **** --- 887,895 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 863,869 **** --- 912,920 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 887,893 **** --- 938,946 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 909,915 **** --- 962,970 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 935,941 **** --- 990,998 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 961,967 **** --- 1018,1026 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 987,993 **** --- 1046,1054 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1008,1014 **** --- 1069,1077 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1032,1038 **** --- 1095,1103 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1068,1074 **** --- 1133,1141 ---- 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO "clo r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1093,1099 **** --- 1160,1168 ---- 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ "clz r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned32 temp = GPR[RS]; *************** *** 1121,1126 **** --- 1190,1196 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1142,1147 **** --- 1212,1218 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1170,1175 **** --- 1241,1247 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1192,1197 **** --- 1264,1270 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1204,1209 **** --- 1277,1283 ---- 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO "dclo r, r" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1228,1233 **** --- 1302,1308 ---- 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ "dclz r, r" *mips64: + *mips64r2: *vr5500: { unsigned64 temp = GPR[RS]; *************** *** 1285,1290 **** --- 1360,1366 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1325,1330 **** --- 1401,1407 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1332,1338 **** --- 1409,1489 ---- do_ddivu (SD_, RS, RT); } + 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT + "dext r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM + "dextm r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU + "dextu r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 010000,01011,5.RT,01100,00000,0,00,000::32::DI + "di":RT == 0 + "di r" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR &= ~status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS + "dins r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM + "dinsm r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB + 32) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU + "dinsu r, r, , " + *mips64r2: + { + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) + & MASK64 (MSB + 32, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); + } :function:::void:do_div:int rs, int rt { *************** *** 1368,1374 **** --- 1519,1527 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1407,1413 **** --- 1560,1568 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1416,1422 **** } - :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p { unsigned64 lo; --- 1571,1576 ---- *************** *** 1488,1493 **** --- 1642,1648 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1516,1521 **** --- 1671,1677 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: { check_u64 (SD_, instruction_0); *************** *** 1531,1536 **** --- 1687,1767 ---- do_dmultu (SD_, RS, RT, RD); } + + :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y + { + unsigned64 result; + + y &= 63; + TRACE_ALU_INPUT2 (x, y); + result = ROTR64 (x, y); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR + "dror r, r, " + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); + } + + 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 + "dror32 r, r, " + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); + } + + 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV + "drorv r, r, r" + *mips64r2: + *vr5400: + *vr5500: + { + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); + } + + + 011111,00000,5.RT,5.RD,00010,100100::64::DSBH + "dsbh r, r" + *mips64r2: + { + union { unsigned64 d; unsigned16 h[4]; } u; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + u.d = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + u.h[2] = SWAP_2 (u.h[2]); + u.h[3] = SWAP_2 (u.h[3]); + GPR[RD] = u.d; + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 011111,00000,5.RT,5.RD,00101,100100::64::DSHD + "dshd r, r" + *mips64r2: + { + unsigned64 d; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + d = GPR[RT]; + GPR[RD] = ((d >> 48) + | (d << 48) + | ((d & 0x0000ffff00000000) >> 16) + | ((d & 0x00000000ffff0000) << 16)); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + :function:::void:do_dsll:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); *************** *** 1544,1549 **** --- 1775,1781 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1558,1563 **** --- 1790,1796 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1582,1587 **** --- 1815,1821 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1603,1608 **** --- 1837,1843 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1617,1622 **** --- 1852,1858 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1642,1647 **** --- 1878,1884 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1663,1668 **** --- 1900,1906 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1677,1682 **** --- 1915,1921 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1704,1709 **** --- 1943,1949 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1718,1723 **** --- 1958,1964 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1745,1750 **** --- 1986,1992 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1753,1758 **** --- 1995,2037 ---- } + 010000,01011,5.RT,01100,00000,1,00,000::32::EI + "ei":RT == 0 + "ei r" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR |= status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); + } + + + 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT + "ext r, r, , " + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + + 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS + "ins r, r, , " + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] = EXTEND32 (GPR[RT] ^ + ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); + TRACE_ALU_RESULT1 (GPR[RT]); + } + + 000010,26.INSTR_INDEX:NORMAL:32::J "j " *mipsI: *************** *** 1761,1767 **** --- 2040,2048 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1781,1787 **** --- 2062,2070 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1802,1808 **** --- 2085,2093 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1821,1827 **** --- 2106,2114 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1948,1954 **** --- 2235,2243 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1965,1971 **** --- 2254,2262 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 1980,1985 **** --- 2271,2277 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 1995,2001 **** --- 2287,2295 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2012,2017 **** --- 2306,2312 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2026,2031 **** --- 2321,2327 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2042,2048 **** --- 2338,2346 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2059,2065 **** --- 2357,2365 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2075,2081 **** --- 2375,2383 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2117,2122 **** --- 2419,2425 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2154,2160 **** --- 2457,2465 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2173,2179 **** --- 2478,2486 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2190,2196 **** --- 2497,2505 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2207,2213 **** --- 2516,2524 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2224,2230 **** --- 2535,2543 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2239,2244 **** --- 2552,2558 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2251,2257 **** --- 2565,2573 ---- 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD "madd r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2271,2277 **** --- 2587,2595 ---- 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU "maddu r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2303,2309 **** --- 2621,2629 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2329,2335 **** --- 2649,2657 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2344,2350 **** --- 2666,2674 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] != 0) *************** *** 2361,2367 **** --- 2685,2693 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { if (GPR[RT] == 0) *************** *** 2376,2382 **** --- 2702,2710 ---- 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB "msub r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 temp; *************** *** 2396,2402 **** --- 2724,2732 ---- 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU "msubu r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { unsigned64 temp; *************** *** 2421,2427 **** --- 2751,2759 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2440,2446 **** --- 2772,2780 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2454,2460 **** --- 2788,2796 ---- 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL "mul r, r, r" *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5500: { signed64 prod; *************** *** 2493,2499 **** --- 2829,2837 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_mult (SD_, RS, RT, 0); *************** *** 2534,2540 **** --- 2872,2880 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: { do_multu (SD_, RS, RT, 0); *************** *** 2565,2571 **** --- 2905,2913 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2589,2595 **** --- 2931,2939 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2614,2620 **** --- 2958,2966 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2628,2634 **** --- 2974,2982 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 2645,2650 **** --- 2993,3030 ---- } + :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y + { + unsigned64 result; + + y &= 31; + TRACE_ALU_INPUT2 (x, y); + result = EXTEND32 (ROTR32 (x, y)); + TRACE_ALU_RESULT (result); + return result; + } + + 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR + "ror r, r, " + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); + } + + 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV + "rorv r, r, r" + *mips32r2: + *mips64r2: + *vr5400: + *vr5500: + { + GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); + } + + :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word { address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); *************** *** 2743,2749 **** --- 3123,3131 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2759,2765 **** --- 3141,3149 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2802,2807 **** --- 3186,3192 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2840,2845 **** --- 3225,3231 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2855,2861 **** --- 3241,3249 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2869,2874 **** --- 3257,3263 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2883,2888 **** --- 3272,3278 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 2891,2896 **** --- 3281,3307 ---- } + 011111,00000,5.RT,5.RD,10000,100000::32::SEB + "seb r, r" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND8 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 011111,00000,5.RT,5.RD,11000,100000::32::SEH + "seh r, r" + *mips32r2: + *mips64r2: + { + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND16 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH "sh r, (r)" *mipsI: *************** *** 2899,2905 **** --- 3310,3318 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2939,2945 **** --- 3352,3360 ---- "ssnop":RD == 0 && RT == 0 && SHIFT == 1 "sll r, r, " *mips32: + *mips32r2: *mips64: + *mips64r2: { /* Skip shift for NOP and SSNOP, so that there won't be lots of extraneous trace output. */ *************** *** 2965,2971 **** --- 3380,3388 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 2989,2995 **** --- 3406,3414 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3013,3019 **** --- 3432,3440 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3037,3043 **** --- 3458,3466 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3062,3068 **** --- 3485,3493 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3089,3095 **** --- 3514,3522 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3118,3124 **** --- 3545,3553 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3146,3152 **** --- 3575,3583 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3174,3180 **** --- 3605,3613 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3191,3197 **** --- 3624,3632 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3225,3231 **** --- 3660,3668 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3242,3248 **** --- 3679,3687 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: *vr5000: *************** *** 3259,3265 **** --- 3698,3706 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3276,3282 **** --- 3717,3725 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3293,3299 **** --- 3736,3744 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3310,3316 **** --- 3755,3763 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3318,3323 **** --- 3765,3777 ---- SyncOperation (STYPE); } + 000001,5.BASE,11111,16.OFFSET::32::SYNCI + "synci (r)" + *mips32r2: + *mips64r2: + { + // sync i-cache - nothing to do currently + } 000000,20.CODE,001100:SPECIAL:32::SYSCALL "syscall %#lx" *************** *** 3327,3333 **** --- 3781,3789 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3343,3349 **** --- 3799,3807 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3359,3365 **** --- 3817,3825 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3375,3381 **** --- 3835,3843 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3391,3397 **** --- 3853,3861 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3407,3413 **** --- 3871,3879 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3423,3429 **** --- 3889,3897 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3439,3445 **** --- 3907,3915 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3455,3461 **** --- 3925,3933 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3471,3477 **** --- 3943,3951 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3487,3493 **** --- 3961,3969 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3503,3509 **** --- 3979,3987 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3519,3525 **** --- 3997,4005 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 3528,3533 **** --- 4008,4028 ---- } + 011111,00000,5.RT,5.RD,00010,100000::32::WSBH + "wsbh r, r" + *mips32r2: + *mips64r2: + { + union { unsigned32 w; unsigned16 h[2]; } u; + TRACE_ALU_INPUT1 (GPR[RT]); + u.w = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + GPR[RD] = EXTEND32 (u.w); + TRACE_ALU_RESULT1 (GPR[RD]); + } + + :function:::void:do_xor:int rs, int rt, int rd { TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); *************** *** 3543,3549 **** --- 4038,4046 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3567,3573 **** --- 4064,4072 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3650,3655 **** --- 4149,4155 ---- *mipsIII: *mipsIV: *mips32: + *mips32r2: *vr4100: *vr5000: *r3900: *************** *** 3663,3668 **** --- 4163,4169 ---- :function:::void:check_fmt_p:int fmt, instruction_word insn *mipsV: *mips64: + *mips64r2: { if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) *************** *** 3683,3689 **** --- 4184,4192 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3703,3708 **** --- 4206,4212 ---- :function:::unsigned64:do_load_double:address_word base, address_word offset *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3739,3744 **** --- 4243,4249 ---- :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v *mipsII: *mips32: + *mips32r2: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; *************** *** 3772,3778 **** --- 4277,4285 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3793,3799 **** --- 4300,4308 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3809,3814 **** --- 4318,4324 ---- "alnv.ps f, f, f, r" *mipsV: *mips64: + *mips64r2: { unsigned64 fs; unsigned64 ft; *************** *** 3868,3874 **** --- 4378,4386 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: #*vr4100: *vr5000: *r3900: *************** *** 3904,3910 **** --- 4416,4424 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3923,3928 **** --- 4437,4443 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3941,3947 **** --- 4456,4464 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 3989,3995 **** --- 4506,4514 ---- "cfc1 r, f" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) *************** *** 4032,4038 **** --- 4551,4559 ---- "ctc1 r, f" *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: { check_fpu (SD_); TRACE_ALU_INPUT1 (GPR[RT]); *************** *** 4053,4059 **** --- 4574,4582 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4073,4078 **** --- 4596,4602 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4090,4095 **** --- 4614,4620 ---- "cvt.ps.s f, f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4109,4115 **** --- 4634,4642 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4127,4132 **** --- 4654,4660 ---- "cvt.s.pl f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4138,4143 **** --- 4666,4672 ---- "cvt.s.pu f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4153,4159 **** --- 4682,4690 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4175,4181 **** --- 4706,4714 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4208,4213 **** --- 4741,4747 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4248,4253 **** --- 4782,4788 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4269,4274 **** --- 4804,4810 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4287,4293 **** --- 4823,4831 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4303,4308 **** --- 4841,4847 ---- "ldc1 f, (r)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); *************** *** 4315,4320 **** --- 4854,4860 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4329,4334 **** --- 4869,4875 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4341,4346 **** --- 4882,4888 ---- "luxc1 f, r(r)" *mipsV: *mips64: + *mips64r2: { address_word base = GPR[BASE]; address_word index = GPR[INDEX]; *************** *** 4362,4368 **** --- 4904,4912 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4377,4382 **** --- 4921,4927 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4391,4396 **** --- 4936,4942 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4420,4426 **** --- 4966,4974 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4430,4435 **** --- 4978,5004 ---- TRACE_ALU_RESULT (GPR[RT]); } + 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 + "mfhc1 r, f" + *mips32r2: + *mips64r2: + { + check_fpu (SD_); + if (SizeFGR() == 64) + GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); + else if ((FS & 0x1) == 0) + GPR[RT] = EXTEND32 (FGR[FS + 1]); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", + (long) CIA); + GPR[RT] = EXTEND32 (0xBADF00D); + } + TRACE_ALU_RESULT (GPR[RT]); + } + 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt "mov.%s f, f" *************** *** 4439,4445 **** --- 5008,5016 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4458,4464 **** --- 5029,5037 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4474,4480 **** --- 5047,5055 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4503,4509 **** --- 5078,5086 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4526,4532 **** --- 5103,5111 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4542,4547 **** --- 5121,5127 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4572,4578 **** --- 5152,5160 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4581,4586 **** --- 5163,5189 ---- StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); } + 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 + "mthc1 r, f" + *mips32r2: + *mips64r2: + { + check_fpu (SD_); + if (SizeFGR() == 64) + StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); + else if ((FS & 0x1) == 0) + StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", + (long) CIA); + StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); + } + TRACE_FP_RESULT (GPR[RT]); + } + 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt "mul.%s f, f, f" *************** *** 4590,4596 **** --- 5193,5201 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4610,4616 **** --- 5215,5223 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4627,4632 **** --- 5234,5240 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4643,4648 **** --- 5251,5257 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4658,4663 **** --- 5267,5273 ---- "pll.ps f, f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4670,4675 **** --- 5280,5286 ---- "plu.ps f, f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4683,4688 **** --- 5294,5300 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { address_word base = GPR[BASE]; *************** *** 4701,4706 **** --- 5313,5319 ---- "pul.ps f, f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4713,4718 **** --- 5326,5332 ---- "puu.ps f, f, f" *mipsV: *mips64: + *mips64r2: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** *** 4726,4731 **** --- 5340,5346 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4740,4745 **** --- 5355,5361 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4758,4764 **** --- 5374,5382 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4775,4780 **** --- 5393,5399 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { int fmt = FMT; *************** *** 4787,4792 **** --- 5406,5412 ---- "sdc1 f, (r)" *mipsII: *mips32: + *mips32r2: { check_fpu (SD_); do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); *************** *** 4799,4804 **** --- 5419,5425 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4813,4818 **** --- 5434,5440 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { check_fpu (SD_); *************** *** 4825,4830 **** --- 5447,5453 ---- "suxc1 f, r(r)" *mipsV: *mips64: + *mips64r2: { unsigned64 v; address_word base = GPR[BASE]; *************** *** 4846,4852 **** --- 5469,5477 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4865,4871 **** --- 5490,5498 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4886,4892 **** --- 5513,5521 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4927,4932 **** --- 5556,5562 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr5000: { *************** *** 4968,4973 **** --- 5598,5604 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 4986,4992 **** --- 5617,5625 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5013,5019 **** --- 5646,5654 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5034,5040 **** --- 5669,5677 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5047,5053 **** --- 5684,5692 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *************** *** 5059,5065 **** --- 5698,5706 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5070,5076 **** --- 5711,5719 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5093,5098 **** --- 5736,5742 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5105,5110 **** --- 5749,5755 ---- *mipsIV: *mipsV: *mips64: + *mips64r2: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** *** 5117,5123 **** --- 5762,5770 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: { *************** *** 5144,5150 **** --- 5791,5799 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5162,5168 **** --- 5811,5819 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *r3900: *************** *** 5194,5200 **** --- 5845,5853 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *r3900: { *************** *** 5211,5217 **** --- 5864,5872 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5224,5230 **** --- 5879,5887 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5237,5243 **** --- 5894,5902 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: *************** *** 5250,5256 **** --- 5909,5917 ---- *mipsIV: *mipsV: *mips32: + *mips32r2: *mips64: + *mips64r2: *vr4100: *vr5000: Index: vr.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/vr.igen,v retrieving revision 1.3 diff -c -p -r1.3 vr.igen *** vr.igen 16 Apr 2003 00:52:08 -0000 1.3 --- vr.igen 9 Nov 2004 15:49:52 -0000 *************** *** 100,134 **** GPR[rd] = store_hi_p ? HI : LO; } - // 32-bit rotate right of X by Y bits. - :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 31; - TRACE_ALU_INPUT2 (x, y); - result = EXTEND32 (ROTR32 (x, y)); - TRACE_ALU_RESULT (result); - return result; - } - - // Likewise 64-bit - :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y - *vr5400: - *vr5500: - { - unsigned64 result; - - y &= 63; - TRACE_ALU_INPUT2 (x, y); - result = ROTR64 (x, y); - TRACE_ALU_RESULT (result); - return result; - } - - // VR4100 instructions. 000000,5.RS,5.RT,00000,00000,101000::32::MADD16 --- 100,105 ---- *************** *** 246,290 **** 0 /* single */); } - 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR - "ror r, r, " - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); - } - - 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV - "rorv r, r, r" - *vr5400: - *vr5500: - { - GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR - "dror r, r, " - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); - } - - 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 - "dror32 r, r, " - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); - } - - 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV - "drorv r, r, r" - *vr5400: - *vr5500: - { - GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); - } 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1 "luxc1 f, r(r)" --- 217,222 ----