From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15445 invoked by alias); 3 Nov 2004 15:26:05 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 15415 invoked from network); 3 Nov 2004 15:26:03 -0000 Received: from unknown (HELO dmz.algor.co.uk) (62.254.210.145) by sourceware.org with SMTP; 3 Nov 2004 15:26:03 -0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1CPN9n-00055p-00 for ; Wed, 03 Nov 2004 15:34:43 +0000 Received: from stockwell.mips.com ([192.168.192.238]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1CPN1L-0004Fg-00 for ; Wed, 03 Nov 2004 15:25:59 +0000 Subject: MIPS32 / MIPS64 release 2 support in simulator From: David Ung To: gdb-patches@sources.redhat.com Content-Type: text/plain Organization: MIPS Technologies UK Message-Id: <1099495559.2778.53.camel@stockwell.mips.com> Mime-Version: 1.0 Date: Wed, 03 Nov 2004 15:26:00 -0000 Content-Transfer-Encoding: 7bit X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam, SpamAssassin (score=-4.852, required 4, AWL, BAYES_00, UPPERCASE_25_50) X-SW-Source: 2004-11/txt/msg00042.txt.bz2 The following file is for MIPS32 / MIPS64 release 2 extensions to the simulator. David. 2004-11-03 David Ung * mips.igen: Added include of m3264r2.igen file. * m3264r2.igen: New file. New instructions for mips32r2 and mips64r2. Index: mips.igen =================================================================== RCS file: /cvs/uberbaum/sim/mips/mips.igen,v retrieving revision 1.57 diff -c -r1.57 mips.igen *** mips.igen 10 Apr 2004 06:51:49 -0000 1.57 --- mips.igen 3 Nov 2004 15:17:41 -0000 *************** *** 5258,5263 **** --- 5258,5264 ---- :include:::m16.igen :include:::mdmx.igen :include:::mips3d.igen + :include:::m3264r2.igen :include:::sb1.igen :include:::tx.igen :include:::vr.igen Index: m3264r2.igen =================================================================== // -*- C -*- // // MIPS32 / MIPS64 release 2 extensions // // TBD: wrpgr, rdpgr, rdhwr 010000,01011,5.RT,01100,00000,0,00,000::32::DI "di":RT == 0 "di r" *mips32,mips64: { GPR[RT] = SR; SR &= ~1; TRACE_ALU_RESULT1 (GPR[RT]); } 010000,01011,5.RT,01100,00000,1,00,000::32::EI "ei":RT == 0 "ei r" *mips32,mips64: { GPR[RT] = SR; SR |= 1; TRACE_ALU_RESULT1 (GPR[RT]); } 000001,5.BASE,11111,16.OFFSET::32::SYNCI "synci (r)" *mips32,mips64: { // sync i-cache - nothing to do currently } 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT "ext r, r, , " *mips32,mips64: { TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT "dext r, r, , " *mips64: { TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM "dextm r, r, , " *mips64: { TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU "dextu r, r, , " *mips64: { TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS "ins r, r, , " *mips32,mips64: { TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] = EXTEND32 (GPR[RT] ^ ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS "dins r, r, , " *mips64: { TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM "dinsm r, r, , " *mips64: { TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB + 32) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); TRACE_ALU_RESULT1 (GPR[RT]); } 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU "dinsu r, r, , " *mips64: { TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); if (LSB <= MSB) GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) & MASK64 (MSB + 32, LSB + 32); TRACE_ALU_RESULT1 (GPR[RT]); } 000000,00001,5.RT,5.RD,5.SA,111010::64::DROTR "drotr r, r, " *mips64: { TRACE_ALU_INPUT2 (GPR[RT], SA); GPR[RD] = ROTR64 (GPR[RT], SA); TRACE_ALU_RESULT1 (GPR[RD]); } 000000,00001,5.RT,5.RD,5.SA,111110::64::DROTR32 "drotr32 r, r, " *mips64: { TRACE_ALU_INPUT2 (GPR[RT], SA); GPR[RD] = ROTR64 (GPR[RT], SA + 32); TRACE_ALU_RESULT1 (GPR[RD]); } 000000,00001,5.RT,5.RD,5.SA,000010::32::ROTR "rotr r, r, " *mips32,mips64: { TRACE_ALU_INPUT2 (GPR[RT], SA); GPR[RD] = EXTEND32 (ROTR32 (GPR[RT], SA)); TRACE_ALU_RESULT1 (GPR[RD]); } 000000,5.RS,5.RT,5.RD,00001,010110::64::DROTRV "drotrv r, r, r" *mips64: { TRACE_ALU_INPUT2 (GPR[RT], GPR[RS]); GPR[RD] = ROTR64 (GPR[RT], GPR[RS] & 0x3f); TRACE_ALU_RESULT1 (GPR[RD]); } 000000,5.RS,5.RT,5.RD,00001,000110::32::ROTRV "rotrv r, r, r" *mips32,mips64: { TRACE_ALU_INPUT2 (GPR[RT], GPR[RS]); GPR[RD] = EXTEND32 (ROTR32 (GPR[RT], GPR[RS] & 0x1f)); TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,00010,100100::64::DSBH "dsbh r, r" *mips64: { union { unsigned64 d; unsigned16 h[4]; } u; TRACE_ALU_INPUT1 (GPR[RT]); u.d = GPR[RT]; u.h[0] = SWAP_2 (u.h[0]); u.h[1] = SWAP_2 (u.h[1]); u.h[2] = SWAP_2 (u.h[2]); u.h[3] = SWAP_2 (u.h[3]); GPR[RD] = u.d; TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,00101,100100::64::DSHD "dshd r, r" *mips64: { unsigned64 d; TRACE_ALU_INPUT1 (GPR[RT]); d = GPR[RT]; GPR[RD] = ((d >> 48) | (d << 48) | ((d >> 16) & 0xffff0000) | ((d & 0xffff0000) << 16)); TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,00010,100000::32::WSBH "wsbh r, r" *mips32,mips64: { union { unsigned32 w; unsigned16 h[2]; } u; TRACE_ALU_INPUT1 (GPR[RT]); u.w = GPR[RT]; u.h[0] = SWAP_2 (u.h[0]); u.h[1] = SWAP_2 (u.h[1]); GPR[RD] = EXTEND32 (u.w); TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,10000,100000::32::SEB "seb r, r" *mips32,mips64: { TRACE_ALU_INPUT1 (GPR[RT]); GPR[RD] = EXTEND8 (GPR[RT]); TRACE_ALU_RESULT1 (GPR[RD]); } 011111,00000,5.RT,5.RD,11000,100000::32::SEH "seh r, r" *mips32,mips64: { TRACE_ALU_INPUT1 (GPR[RT]); GPR[RD] = EXTEND16 (GPR[RT]); TRACE_ALU_RESULT1 (GPR[RD]); } 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32::MFHC1 "mfhc1 r, f" *mips32,mips64: { if (SizeFGR() == 64) GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); else if ((FS & 0x1) == 0) GPR[RT] = EXTEND32 (FGR[FS + 1]); else { if (STATE_VERBOSE_P(SD)) sim_io_eprintf (SD, "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", (long) CIA); GPR[RT] = EXTEND32 (0xBADF00D); } } 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32::MTHC1 "mthc1 r, f" *mips32,mips64: { if (SizeFGR() == 64) StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); else if ((FS & 0x1) == 0) StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); else { if (STATE_VERBOSE_P(SD)) sim_io_eprintf (SD, "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", (long) CIA); StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); } }