Question about YMM register availability in x86 CPUs

Question about YMM register availability in x86 CPUs

[Guinevere Larsen via Gdb]

Hello gdb list!

TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX 
capabilities will have both XMM and YMM registers?

Some background, I'm trying to implement record full support for AVX and 
AVX2 instructions. As part of this effort, I have to decide when we 
should record the full YMM (or ZMM if available) and when we should 
record just XMM. This had me wondering if I can just decide to always 
record YMM registers, or if I need to query avx-capable targets about 
whether they have those registers.

At least at some points I am pretty sure I should record the biggest 
vector register available since, for example, vmovd/vmovq will overwrite 
all higher bits, so we'll lose information if we just use the provided 
register instead of recording the full size of register available.

Looking at gdb/amd64-tdep.c, it seems like ymm can be assumed, as on 
lines 3193-3197 we seem to set the number of available ymm registers 
just by looking for avx, and not checking for avx2 at all, but I wanted 
to see if anyone could say for certain, not just me extrapolating from 
code I don't really understand :)

-- 
Cheers,
Guinevere Larsen
She/Her/Hers

RE: Question about YMM register availability in x86 CPUs

[Willgerodt, Felix via Gdb]

> -----Original Message-----
> From: Gdb <gdb-bounces+felix.willgerodt=intel.com@sourceware.org> On Behalf
> Of Guinevere Larsen via Gdb
> Sent: Mittwoch, 12. Juni 2024 22:31
> To: gdb@sourceware.org
> Subject: Question about YMM register availability in x86 CPUs
> 
> Hello gdb list!
> 
> TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX
> capabilities will have both XMM and YMM registers?
> 

Hi Guinivere,

The Intel Software Development Manual tells you about AVX
in Volume 1, Chapter 14.1.1:

"Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7
in operating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode).
The lower 128-bits of the YMM registers are aliased to the respective 128-bit
XMM registers"

In chapter 14.6.1 it tells you what AVX2 added. It is just extending old
instructions to 256 bit and adding new ones. No new register space.

So I think yes it is reasonable to assume that.

Regards,
Felix


Intel Deutschland GmbH
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Re: Question about YMM register availability in x86 CPUs

[Guinevere Larsen via Gdb]

On 6/13/24 10:19 AM, Willgerodt, Felix wrote:
>> -----Original Message-----
>> From: Gdb <gdb-bounces+felix.willgerodt=intel.com@sourceware.org> On Behalf
>> Of Guinevere Larsen via Gdb
>> Sent: Mittwoch, 12. Juni 2024 22:31
>> To: gdb@sourceware.org
>> Subject: Question about YMM register availability in x86 CPUs
>>
>> Hello gdb list!
>>
>> TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX
>> capabilities will have both XMM and YMM registers?
>>
> Hi Guinivere,
>
> The Intel Software Development Manual tells you about AVX
> in Volume 1, Chapter 14.1.1:
>
> "Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7
> in operating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode).
> The lower 128-bits of the YMM registers are aliased to the respective 128-bit
> XMM registers"
>
> In chapter 14.6.1 it tells you what AVX2 added. It is just extending old
> instructions to 256 bit and adding new ones. No new register space.
>
> So I think yes it is reasonable to assume that.
>
Hi Felix,

Thank you for confirming this for me! I'll keep this in mind for future 
AVX recording development.

-- 
Cheers,
Guinevere Larsen
She/Her/Hers