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([2804:14d:8084:92c5::1001]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7955afa4057sm385804985a.47.2024.06.12.13.31.02 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Jun 2024 13:31:03 -0700 (PDT) Message-ID: <1ea5f9b9-3e73-4d51-ae77-fe0d1f77a161@redhat.com> Date: Wed, 12 Jun 2024 17:31:00 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: gdb@sourceware.org Subject: Question about YMM register availability in x86 CPUs X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Guinevere Larsen via Gdb Reply-To: Guinevere Larsen Errors-To: gdb-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb" Hello gdb list! TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX capabilities will have both XMM and YMM registers? Some background, I'm trying to implement record full support for AVX and AVX2 instructions. As part of this effort, I have to decide when we should record the full YMM (or ZMM if available) and when we should record just XMM. This had me wondering if I can just decide to always record YMM registers, or if I need to query avx-capable targets about whether they have those registers. At least at some points I am pretty sure I should record the biggest vector register available since, for example, vmovd/vmovq will overwrite all higher bits, so we'll lose information if we just use the provided register instead of recording the full size of register available. Looking at gdb/amd64-tdep.c, it seems like ymm can be assumed, as on lines 3193-3197 we seem to set the number of available ymm registers just by looking for avx, and not checking for avx2 at all, but I wanted to see if anyone could say for certain, not just me extrapolating from code I don't really understand :) -- Cheers, Guinevere Larsen She/Her/Hers