From: "Willgerodt, Felix via Gdb" <gdb@sourceware.org>
To: Guinevere Larsen <blarsen@redhat.com>,
"gdb@sourceware.org" <gdb@sourceware.org>
Subject: RE: Question about YMM register availability in x86 CPUs
Date: Thu, 13 Jun 2024 13:19:42 +0000 [thread overview]
Message-ID: <MN2PR11MB45664E234615766D5EB9AF888EC12@MN2PR11MB4566.namprd11.prod.outlook.com> (raw)
In-Reply-To: <1ea5f9b9-3e73-4d51-ae77-fe0d1f77a161@redhat.com>
> -----Original Message-----
> From: Gdb <gdb-bounces+felix.willgerodt=intel.com@sourceware.org> On Behalf
> Of Guinevere Larsen via Gdb
> Sent: Mittwoch, 12. Juni 2024 22:31
> To: gdb@sourceware.org
> Subject: Question about YMM register availability in x86 CPUs
>
> Hello gdb list!
>
> TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX
> capabilities will have both XMM and YMM registers?
>
Hi Guinivere,
The Intel Software Development Manual tells you about AVX
in Volume 1, Chapter 14.1.1:
"Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7
in operating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode).
The lower 128-bits of the YMM registers are aliased to the respective 128-bit
XMM registers"
In chapter 14.6.1 it tells you what AVX2 added. It is just extending old
instructions to 256 bit and adding new ones. No new register space.
So I think yes it is reasonable to assume that.
Regards,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
next prev parent reply other threads:[~2024-06-13 13:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 20:31 Guinevere Larsen via Gdb
2024-06-13 13:19 ` Willgerodt, Felix via Gdb [this message]
2024-06-13 14:04 ` Guinevere Larsen via Gdb
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