From: Guinevere Larsen via Gdb <gdb@sourceware.org>
To: "Willgerodt, Felix" <felix.willgerodt@intel.com>,
"gdb@sourceware.org" <gdb@sourceware.org>
Subject: Re: Question about YMM register availability in x86 CPUs
Date: Thu, 13 Jun 2024 11:04:12 -0300 [thread overview]
Message-ID: <a80b8eed-b220-4bba-a472-24bc9952d98c@redhat.com> (raw)
In-Reply-To: <MN2PR11MB45664E234615766D5EB9AF888EC12@MN2PR11MB4566.namprd11.prod.outlook.com>
On 6/13/24 10:19 AM, Willgerodt, Felix wrote:
>> -----Original Message-----
>> From: Gdb <gdb-bounces+felix.willgerodt=intel.com@sourceware.org> On Behalf
>> Of Guinevere Larsen via Gdb
>> Sent: Mittwoch, 12. Juni 2024 22:31
>> To: gdb@sourceware.org
>> Subject: Question about YMM register availability in x86 CPUs
>>
>> Hello gdb list!
>>
>> TL;DR: Is it reasonable to assume that all x86 CPUs that have AVX
>> capabilities will have both XMM and YMM registers?
>>
> Hi Guinivere,
>
> The Intel Software Development Manual tells you about AVX
> in Volume 1, Chapter 14.1.1:
>
> "Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7
> in operating modes that are 32-bit or less, YMM0-YMM15 in 64-bit mode).
> The lower 128-bits of the YMM registers are aliased to the respective 128-bit
> XMM registers"
>
> In chapter 14.6.1 it tells you what AVX2 added. It is just extending old
> instructions to 256 bit and adding new ones. No new register space.
>
> So I think yes it is reasonable to assume that.
>
Hi Felix,
Thank you for confirming this for me! I'll keep this in mind for future
AVX recording development.
--
Cheers,
Guinevere Larsen
She/Her/Hers
prev parent reply other threads:[~2024-06-13 14:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 20:31 Guinevere Larsen via Gdb
2024-06-13 13:19 ` Willgerodt, Felix via Gdb
2024-06-13 14:04 ` Guinevere Larsen via Gdb [this message]
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