* [PATCH] make MIPS sim mips.igen model names one per line.
@ 2002-02-11 12:26 cgd
2002-02-11 13:18 ` Frank Ch. Eigler
0 siblings, 1 reply; 7+ messages in thread
From: cgd @ 2002-02-11 12:26 UTC (permalink / raw)
To: cagney, gdb-patches
[ Andrew, I've not committed this yet. As sim/mips co-maintainer, if
you'd like to do otherwise, I'd like to hear your argument... ]
So, right now, the mips.igen file names models supported by
instructions in one of two ways:
111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*vr4100:
*vr5000:
*r3900:
or:
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr4100:
*vr5000:
*r3900:
(i.e., one per line, or all MIPS ISAs in one line and the rest one per
line.)
In our local source tree, we've converted it to use only the former
form. I think it's the right thing from a maintainability (fewer
conflicts/patched lines) and consistency perspective (should convert
to be consistent one way or another).
I also asked Eric C. what he thought The Right Thing is, and he agrees
that going with one per line universally is the right thing.
IMO, the alternative is to list all of the MIPS ISAs in one line,
consistently. That's harder to do.
It may be worth noting that MIPS is currently the only set of igen
files (that i could grep 8-) that list multiple model names on a
single line. Of course, it has by far the most supported model names,
too.
Andrew, do you have any thoughs/objections?
cgd
===================================================================
2002-02-11 Chris Demetriou <cgd@broadcom.com>
* mips.igen: For all function and instructions, list model
names that support that instruction one per line.
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.9
diff -u -r1.9 mips.igen
--- mips.igen 2002/02/11 06:13:49 1.9
+++ mips.igen 2002/02/11 20:12:01
@@ -115,7 +115,10 @@
}
:function:::int:check_mt_hilo:hilo_history *history
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
{
@@ -137,7 +140,10 @@
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -169,7 +175,10 @@
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
{
@@ -199,7 +208,10 @@
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -228,7 +240,10 @@
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -246,7 +261,10 @@
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -271,7 +289,10 @@
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -290,7 +311,10 @@
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -309,7 +333,10 @@
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -321,7 +348,10 @@
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -335,7 +365,10 @@
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -375,7 +408,10 @@
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -393,7 +429,10 @@
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -459,7 +498,10 @@
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -501,7 +543,10 @@
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -543,7 +588,10 @@
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -561,7 +609,10 @@
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -629,7 +680,10 @@
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -669,7 +723,10 @@
000000,20.CODE,001101:SPECIAL:32::BREAK
"break <CODE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -884,7 +941,10 @@
000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -917,7 +977,10 @@
000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -994,7 +1057,8 @@
000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
*vr4100:
{
do_dmult (SD_, RS, RT, 0);
@@ -1017,7 +1081,8 @@
000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
*vr4100:
{
do_dmultu (SD_, RS, RT, 0);
@@ -1207,7 +1272,10 @@
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1221,7 +1289,10 @@
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1236,7 +1307,10 @@
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1249,7 +1323,10 @@
000000,5.RS,000000000000000,001000:SPECIAL:32::JR
"jr r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1284,7 +1361,10 @@
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1295,7 +1375,10 @@
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1354,7 +1437,10 @@
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1365,7 +1451,10 @@
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1452,7 +1541,10 @@
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1465,7 +1557,10 @@
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1476,7 +1571,10 @@
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1544,7 +1642,10 @@
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1586,7 +1687,10 @@
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1616,7 +1720,10 @@
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1636,7 +1743,10 @@
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1670,7 +1780,10 @@
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1683,7 +1796,10 @@
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1710,7 +1826,10 @@
000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
@@ -1743,7 +1862,10 @@
000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
@@ -1768,7 +1890,10 @@
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1786,7 +1911,10 @@
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1805,7 +1933,10 @@
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1859,7 +1990,10 @@
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -1994,7 +2128,10 @@
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2014,7 +2151,10 @@
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2037,7 +2177,10 @@
000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2055,7 +2198,10 @@
000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2073,7 +2219,10 @@
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2091,7 +2240,10 @@
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2110,7 +2262,10 @@
000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2129,7 +2284,10 @@
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2150,7 +2308,10 @@
000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2170,7 +2331,10 @@
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2190,7 +2354,10 @@
000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2201,7 +2368,10 @@
000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2225,7 +2395,10 @@
000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2236,7 +2409,10 @@
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*r3900:
*vr5000:
@@ -2247,7 +2423,10 @@
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2305,7 +2484,10 @@
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2337,7 +2519,10 @@
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2362,7 +2547,10 @@
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2536,7 +2724,10 @@
000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2554,7 +2745,10 @@
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2635,7 +2829,10 @@
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2656,7 +2853,10 @@
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2683,7 +2883,9 @@
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
-*mipsI,mipsII,mipsIII:
+*mipsI:
+*mipsII:
+*mipsIII:
{
check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
@@ -2773,7 +2975,9 @@
010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII:
+*mipsI:
+*mipsII:
+*mipsIII:
{
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
@@ -2909,7 +3113,10 @@
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2953,7 +3160,10 @@
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2973,7 +3183,10 @@
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -2993,7 +3206,10 @@
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3145,7 +3361,10 @@
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3241,7 +3460,10 @@
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3356,7 +3578,10 @@
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3377,7 +3602,10 @@
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3607,7 +3835,10 @@
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3629,7 +3860,10 @@
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
@@ -3755,7 +3989,10 @@
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
@@ -3770,20 +4007,29 @@
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
@@ -3811,14 +4057,18 @@
010000,1,0000000000000000000,111001:COP0:32::DI
"di"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
{
DecodeCoproc (instruction_0);
}
@@ -3826,7 +4076,8 @@
010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
{
DecodeCoproc (instruction_0);
}
@@ -3834,7 +4085,10 @@
010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
@@ -3863,7 +4117,10 @@
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*r3900:
*vr4100:
*vr5000:
@@ -3875,7 +4132,10 @@
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*r3900:
*vr4100:
*vr5000:
@@ -3886,7 +4146,10 @@
010000,1,0000000000000000000,010000:COP0:32::RFE
"rfe"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*r3900:
*vr4100:
*vr5000:
@@ -3897,7 +4160,10 @@
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*r3900:
{
@@ -3908,28 +4174,40 @@
010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
*vr4100:
*vr5000:
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-11 12:26 [PATCH] make MIPS sim mips.igen model names one per line cgd
@ 2002-02-11 13:18 ` Frank Ch. Eigler
2002-02-11 13:44 ` cgd
0 siblings, 1 reply; 7+ messages in thread
From: Frank Ch. Eigler @ 2002-02-11 13:18 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> [...]
> So, right now, the mips.igen file names models supported by
> instructions in one of two ways:
> [...]
> (i.e., one per line, or all MIPS ISAs in one line and the rest one per
> line.)
>
> In our local source tree, we've converted it to use only the former
> form. I think it's the right thing from a maintainability (fewer
> conflicts/patched lines) and consistency perspective (should convert
> to be consistent one way or another).
> [...]
I must admit I don't see the point of this specific grasp for
consistency. The single-line format allows compactness; the
multi-line format allows greps and other line-by-line source
manipulations. These are both useful in their place.
Have you actually encountered the maintainability issues you mention
([more?] "conflicts/patched lines")? Were they really troublesome?
Given the preferred use of context diffs, it doesn't seem like
A
B
CHANGE
D
E
is any less likely to get conflicts than
A,B
CHANGE
D,E
- FChE
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-11 13:18 ` Frank Ch. Eigler
@ 2002-02-11 13:44 ` cgd
2002-02-11 13:58 ` Andrew Cagney
0 siblings, 1 reply; 7+ messages in thread
From: cgd @ 2002-02-11 13:44 UTC (permalink / raw)
To: fche; +Cc: gdb-patches
At 11 Feb 2002 16:18:47 -0500, fche@redhat.com wrote:
> cgd@broadcom.com writes:
> I must admit I don't see the point of this specific grasp for
> consistency. The single-line format allows compactness; the
> multi-line format allows greps and other line-by-line source
> manipulations. These are both useful in their place.
In this case, I fail to see how _mixing_ them in mips.igen for a
single set of ISAs (the standars mipsI ... mipsIV, and soon to be
mips32, mips64), is the right thing.
One way or the other, I think it should be consistent at least for the
MIPS ISA 'models'. There's no reason to have inconsistency.
> Have you actually encountered the maintainability issues you mention
> ([more?] "conflicts/patched lines")? Were they really troublesome?
> Given the preferred use of context diffs, it doesn't seem like
>
> A
> B
> CHANGE
> D
> E
>
> is any less likely to get conflicts than
>
> A,B
> CHANGE
> D,E
I think we've seen _a little_ in terms of that, but really it's not
been _too_ large a problem because, uh, hardly anybody has changed the
code in a long time. 8-)
I think I've heard some people (at RH, adding new model names to the
sim stuff) indicate that one-per-line is better for them. That was
like a year and a quarter ago, though, so maybe i'm misremembering.
It can actually help in practice to reduce cvs merge conflicts.
Consider:
A
B
C
modified by one person to be:
A
NEW_1
B
C
and modified by another to be:
A
B
NEW_2
C
CVS will resolve properly w/o a conflict.
in mips.igen, there typically _will_ be lines between added model name
lines, because normally you have:
<mips isas, one per line or many per line>
<one vendor's models>
<another vendor's models>
<another vendor's models>
etc. and often if you're working independently you're adding things to
different vendor model lists. (Of course, as it is now, those are
already one-per-line.)
So, in a nutshell:
(1) it can help some in general,
(2) the place where it would help most is already one-per-line,
(3) right now, for the stock MIPS ISAs 'models', the usage is mixed,
and there's no reason for that.
(4) there _is_ a bit of benefit to having one per-line even for the
stock MIPS ISAs. Eric's going to be folding in the mips32/mips64
stuff soon. I've got similar changes, and also mipsV changes. So
there will be some merging in the future, and having one-per-line
will help there.
Also, it's not as easy to go the other way than it is to split things
to be one per line. (My change was constructed via: :g/^\*/s;,;:^M*;g
Going the other way isn't so easy. 8-)
chris
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-11 13:44 ` cgd
@ 2002-02-11 13:58 ` Andrew Cagney
2002-02-12 15:26 ` cgd
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Cagney @ 2002-02-11 13:58 UTC (permalink / raw)
To: cgd; +Cc: fche, gdb-patches
>
> In this case, I fail to see how _mixing_ them in mips.igen for a
> single set of ISAs (the standars mipsI ... mipsIV, and soon to be
> mips32, mips64), is the right thing.
>
> One way or the other, I think it should be consistent at least for the
> MIPS ISA 'models'. There's no reason to have inconsistency.
Yes, the debate over this patch occured long ago. My memory is that it
was agreed that the standard MIPS defined variants should all appear on
a single line but specific ISA implementations got to have their own line
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-11 13:58 ` Andrew Cagney
@ 2002-02-12 15:26 ` cgd
2002-02-12 16:31 ` Andrew Cagney
0 siblings, 1 reply; 7+ messages in thread
From: cgd @ 2002-02-12 15:26 UTC (permalink / raw)
To: Andrew Cagney; +Cc: fche, gdb-patches
At Mon, 11 Feb 2002 16:58:51 -0500, Andrew Cagney wrote:
> > In this case, I fail to see how _mixing_ them in mips.igen for a
> > single set of ISAs (the standars mipsI ... mipsIV, and soon to be
> > mips32, mips64), is the right thing.
> >
> > One way or the other, I think it should be consistent at least for the
> > MIPS ISA 'models'. There's no reason to have inconsistency.
>
> Yes, the debate over this patch occured long ago. My memory is that it
> was agreed that the standard MIPS defined variants should all appear on
> a single line but specific ISA implementations got to have their own line
If that's the way people want to go, I can do that, but:
(1) that is directly in opposition to what you indicated was your
preference in December 2000 (see the mail I fwded you 8-), and
(2) I think it'll be easier for Eric to do his mips32/mips64 merge,
then subsequently for me to merge the mipsV changes we have here,
if it's one-per-line. (In addition to being esier to get the file
into the one-per-line state to begin with. 8-)
I just want agreement one way or another, so i can make it so. 8-)
cgd
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-12 15:26 ` cgd
@ 2002-02-12 16:31 ` Andrew Cagney
2002-02-19 0:10 ` cgd
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Cagney @ 2002-02-12 16:31 UTC (permalink / raw)
To: cgd; +Cc: fche, gdb-patches
> Yes, the debate over this patch occured long ago. My memory is that it
>> was agreed that the standard MIPS defined variants should all appear on
>> a single line but specific ISA implementations got to have their own line
>
>
> If that's the way people want to go, I can do that, but:
>
> (1) that is directly in opposition to what you indicated was your
> preference in December 2000 (see the mail I fwded you 8-), and
That long ago!
> (2) I think it'll be easier for Eric to do his mips32/mips64 merge,
> then subsequently for me to merge the mipsV changes we have here,
> if it's one-per-line. (In addition to being esier to get the file
> into the one-per-line state to begin with. 8-)
>
With 20:20 hindsite, I really do not care :-) If life will be easier
for Eric then yes, separate lines.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] make MIPS sim mips.igen model names one per line.
2002-02-12 16:31 ` Andrew Cagney
@ 2002-02-19 0:10 ` cgd
0 siblings, 0 replies; 7+ messages in thread
From: cgd @ 2002-02-19 0:10 UTC (permalink / raw)
To: Andrew Cagney; +Cc: fche, gdb-patches
At Tue, 12 Feb 2002 19:30:59 -0500, Andrew Cagney wrote:
> With 20:20 hindsite, I really do not care :-) If life will be easier
> for Eric then yes, separate lines.
This was where we left it a week ago. I think it's the right thing.
I just checked it in.
cgd
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2002-02-19 8:10 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-02-11 12:26 [PATCH] make MIPS sim mips.igen model names one per line cgd
2002-02-11 13:18 ` Frank Ch. Eigler
2002-02-11 13:44 ` cgd
2002-02-11 13:58 ` Andrew Cagney
2002-02-12 15:26 ` cgd
2002-02-12 16:31 ` Andrew Cagney
2002-02-19 0:10 ` cgd
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