From: Peter Bergner <bergner@vnet.ibm.com>
To: Ulrich Weigand <uweigand@de.ibm.com>
Cc: Pedro Alves <palves@redhat.com>, Alan Modra <amodra@gmail.com>,
gdb-patches@sourceware.org,
binutils <binutils@sourceware.org>
Subject: Re: [PATCH, RFC] Add support for choosing disassembler cpu in GDB for POWER.
Date: Fri, 28 Oct 2016 15:02:00 -0000 [thread overview]
Message-ID: <afb86945-7024-c7e1-c966-e120480eded7@vnet.ibm.com> (raw)
In-Reply-To: <20161028141511.5B39E10B91A@oc8523832656.ibm.com>
On 10/28/16 9:15 AM, Ulrich Weigand wrote:
> It's probably not that important to exactly match objdump
> behavior here. B.t.w. how do you even enter a space as
> separator with the -M option?
bergner@genoa:~$ objdump -d -M'power5 power6' wait.o | grep warning
warning: ignoring unknown -Mpower5 power6 option
> I thought rather that it would be preferable to refactor the
> objdump code first, so that even in objdump, there is already
> a generic printing routine that simply works on a list of
> option name / description pairs provided by the target back-end.
>
> Then we could simply make that list of option name / description
> pairs available to GDB and use it in a GDB generic print routine
> that then automatically looks similar to the native objdump
> help output.
But not all arches have descriptions paired with the option name.
Looking at Pedro's objdump output from before:
The following ARM specific disassembler options are supported for use with
the -M switch:
reg-names-special-atpcs Select special register names used in the ATPCS
reg-names-atpcs Select register names used in the ATPCS
reg-names-apcs Select register names used in the APCS
reg-names-std Select register names used in ARM's ISA documentation
reg-names-gcc Select register names used by GCC
reg-names-raw Select raw register names
force-thumb Assume all insns are Thumb insns
no-force-thumb Examine preceding label to determine an insn's type
This would work well for what you propose, but on power, we just dump them out:
The following PPC specific disassembler options are supported for use with
the -M switch:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455,
750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com,
e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, power4,
power5, power6, power7, power8, power9, ppc, ppc32, ppc64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx,
spe, titan, vle, vsx, htm, 32, 64
I wouldn't want all of those cpus dumped out on one line apiece ala:
The following PPC specific disassembler options are supported for use with
the -M switch:
403
405
440
464
476
601
...
That would get very long!
Peter
next prev parent reply other threads:[~2016-10-28 15:02 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-30 2:14 Peter Bergner
2016-09-30 17:55 ` Ulrich Weigand
2016-10-03 20:25 ` Peter Bergner
2016-10-03 22:25 ` Alan Modra
2016-10-06 3:00 ` Peter Bergner
2016-10-06 4:44 ` Alan Modra
2016-10-06 9:52 ` Pedro Alves
2016-10-06 19:26 ` Peter Bergner
2016-10-07 19:21 ` Ulrich Weigand
2016-10-07 21:01 ` Peter Bergner
2016-10-08 14:39 ` Ulrich Weigand
2016-10-10 23:28 ` Peter Bergner
2016-10-12 8:08 ` Ulrich Weigand
2016-10-12 10:46 ` Pedro Alves
2016-10-11 0:09 ` Pedro Alves
2016-10-11 18:49 ` Peter Bergner
2016-10-12 8:25 ` Ulrich Weigand
2016-10-27 0:04 ` Peter Bergner
2016-10-27 9:40 ` Pedro Alves
2016-10-28 13:47 ` Peter Bergner
2016-10-28 14:10 ` Pedro Alves
2016-10-28 14:24 ` Peter Bergner
2016-10-28 14:30 ` Pedro Alves
2016-10-28 14:53 ` Peter Bergner
2016-11-03 11:01 ` Pedro Alves
2016-11-03 15:02 ` Peter Bergner
2016-11-03 15:06 ` Peter Bergner
2016-11-03 16:41 ` Ulrich Weigand
2016-11-03 16:49 ` Peter Bergner
2016-10-28 12:32 ` Ulrich Weigand
2016-10-28 13:45 ` Peter Bergner
2016-10-28 14:15 ` Ulrich Weigand
2016-10-28 15:02 ` Peter Bergner [this message]
2016-10-28 18:47 ` Ulrich Weigand
2016-11-02 23:28 ` Peter Bergner
2016-10-12 19:35 ` Pedro Alves
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