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* Re: [patch rfc] Add NUM_REGS pseudo regs to MIPS
@ 2003-07-21 22:57 Steve Watt
  2003-07-27 13:50 ` [patch rfc, 6.0?] only allow raw raw registers; Was: " Andrew Cagney
  0 siblings, 1 reply; 10+ messages in thread
From: Steve Watt @ 2003-07-21 22:57 UTC (permalink / raw)
  To: Andrew Cagney, Steve Watt; +Cc: gdb-patches

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On Jul 21, 18:07, Andrew Cagney wrote:
} Subject: Re: [patch rfc] Add NUM_REGS pseudo regs to MIPS
} 
} > (top-gdb) info stack
} > #0  internal_error (file=0x824e580 "../../combined/gdb/mips-tdep.c", line=5671, 
} >     string=0x824e555 "%s: Assertion `%s' failed.") at ../../combined/gdb/utils.c:807
} > #1  0x080dd45c in mips_register_sim_regno (regnum=90)
} >     at ../../combined/gdb/mips-tdep.c:5671
} > #2  0x080cb037 in gdbarch_register_sim_regno (gdbarch=0x83179d8, reg_nr=90)
} >     at ../../combined/gdb/gdbarch.c:3983
} > #3  0x08127e0f in gdbsim_fetch_register (regno=90) at ../../combined/gdb/remote-sim.c:299
} > #4  0x08094450 in legacy_read_register_gen (regnum=90, 
} >     myaddr=0xbffff0f0 "Ððÿ¿Øy1\b\030ñÿ¿\020\227\f\bØy1\bZ")
} >     at ../../combined/gdb/regcache.c:730
} > #5  0x0809453e in regcache_raw_read (regcache=0x8323000, regnum=90, buf=0xbffff0f0)
} >     at ../../combined/gdb/regcache.c:748
} > #6  0x0809499a in regcache_cooked_read (regcache=0x8323000, regnum=90, buf=0xbffff0f0)
} >     at ../../combined/gdb/regcache.c:838
} 
} It went wrong here.  It tests (regnum < ->nr_raw_registers), but for 
} legacy targets NR_RAW_REGISTERS == NUM_REGS + NUM_PSEUDO_REGS :-(
} 
} The correct fix is to just delete a heap of code, however ...
} 
}  From regcache.c:
} 
} >   if ((!gdbarch_pseudo_register_read_p (gdbarch)
} >        && !gdbarch_pseudo_register_write_p (gdbarch)
} >        && !gdbarch_register_type_p (gdbarch))
} >       || REGISTER_BYTE_P () || REGISTER_RAW_SIZE_P ())
} >     {
} >       descr->legacy_p = 1;
} >       init_legacy_regcache_descr (gdbarch, descr);
} >       return descr;
} >     }
} 
} can you try removing the two || ... clauses I added 2003-07-03?
} 
} I think my change may have fixed some legacy code but broke others :-(

Well, that fixes it.  That's my favorite kind of bug fix, but also my
favorite (not!) kind of repercussion.

At least I've got a toy I can play with again!

Thanks for the help, and good luck on the Right Fix.  Let me know if
there's something more you want checked.


Steve

-- 
Steve Watt       KD6GGD  PP-ASEL-IA       Email at  home: steve@watt.com
Chelsio Communications   http://www.chelsio.com/    work: steve@chelsio.com
510 N. Pastoria Ave                                Voice: +1 408 962 3627
Sunnyvale, CA, USA, 94085                            Fax: +1 408 730 2580


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [patch rfc, 6.0?] only allow raw raw registers; Was: [patch rfc] Add NUM_REGS pseudo regs to MIPS
@ 2003-07-27 18:55 Steve Watt
  2003-07-27 21:23 ` Andrew Cagney
  0 siblings, 1 reply; 10+ messages in thread
From: Steve Watt @ 2003-07-27 18:55 UTC (permalink / raw)
  To: Andrew Cagney, gdb-patches

On Jul 27,  9:50, Andrew Cagney wrote:
} Subject: [patch rfc, 6.0?] only allow raw raw registers; Was: [patch rfc] 
} 
} Hello,
} 
} The attached hopefully fixes the panic that SteveW was noticing with the 
} MIPS GNU/Linux target.   It chops the legacy register cache (which the 
} MIPS uses) back so that it can no longer contain pseudo registers.
} 
} Working through the build list, it has the potential of also affecting:
} 
} h8300hms:gdbarch_dump: NUM_PSEUDO_REGS = 1
} i386-elf:gdbarch_dump: NUM_PSEUDO_REGS = 8
} m68hc11-elf:gdbarch_dump: NUM_PSEUDO_REGS = 37
} mips-elf:gdbarch_dump: NUM_PSEUDO_REGS = 90
} x86_64-linux-gnu:gdbarch_dump: NUM_PSEUDO_REGS = 8
} 
} (and sh64)
} 
} but since everything is now using pseudo register read/write, instead of 
} fetch/store pseudo register (I deleted that), it should ho longer have 
} any affect.
} 
} Hmm, if fetch/store pseudo is deleted all sorts of code can go ....
} 
} Steve, does this fix your problem?  Assuming it does, I'll also look to 
} commit this to the 6.0 branch.

How about halfway?  It fixes the abort, but leaves a weirdo in the
output:

(steve@mustang) 48> ./gdb /users/steve/tmp/t/hello.mips
GNU gdb 2003-07-27-cvs
Copyright 2003 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB.  Type "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=mips-elf"...
Setting up the environment for debugging gdb.
.gdbinit:5: Error in sourced command file:
Function "internal_error" not defined.
(gdb) target sim
Connected to the simulator.
(gdb) load
Loading section .text, size 0x150c vma 0xa0020000
Loading section .init, size 0x38 vma 0xa002150c
Loading section .fini, size 0x28 vma 0xa0021544
Loading section .sdata, size 0x14 vma 0xa0021d20
Loading section .ctors, size 0x8 vma 0xa002156c
Loading section .dtors, size 0x8 vma 0xa0021574
Loading section .rodata, size 0x2 vma 0xa002157c
Loading section .eh_frame, size 0x4 vma 0xa0021580
Loading section .data, size 0x790 vma 0xa0021588
Loading section .jcr, size 0x4 vma 0xa0021d18
Start address 0xa0020004
Transfer rate: 59728 bits in <1 sec.
(gdb) break _start
Breakpoint 1 at 0xa0020004: file ../../../../combined/libgloss/mips/crt0.S, line 74.
(gdb) run
Starting program: /users/steve/tmp/t/hello.mips

Breakpoint 1, _start () at ../../../../combined/libgloss/mips/crt0.S:74
74              li      v0, STATUS_MASK
Current language:  auto; currently asm
(gdb) info regs
Undefined info command: "regs".  Try "help info".
(gdb) info regi
          zero       at       v0       v1       a0       a1       a2       a3
 R90  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
            t0       t1       t2       t3       t4       t5       t6       t7
 R98  00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
            s0       s1       s2       s3       s4       s5       s6       s7
 R106 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
            t8       t9       k0       k1       gp       sp       s8       ra
 R114 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
            sr       lo       hi      bad    cause       pc
      00400004 00000000 00000000 00000000 00000000 a0020004
           fsr      fir
      00000000 00000000
(gdb)

It's displaying stuff (and further runs appear correct), but the register
number in the left column needs 90 subtracted.  (Well, I'm sure there's
a real fix, but...)

So far, so good.

-- 
Steve Watt       KD6GGD  PP-ASEL-IA       Email at  home: steve@watt.com
Chelsio Communications   http://www.chelsio.com/    work: steve@chelsio.com
510 N. Pastoria Ave                                Voice: +1 408 962 3627
Sunnyvale, CA, USA, 94085                            Fax: +1 408 730 2580


^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2003-08-20 16:44 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-07-21 22:57 [patch rfc] Add NUM_REGS pseudo regs to MIPS Steve Watt
2003-07-27 13:50 ` [patch rfc, 6.0?] only allow raw raw registers; Was: " Andrew Cagney
2003-07-27 18:55 Steve Watt
2003-07-27 21:23 ` Andrew Cagney
2003-07-28 15:37   ` Andrew Cagney
2003-07-28 16:38     ` Daniel Jacobowitz
2003-08-18 17:09       ` Daniel Jacobowitz
2003-08-18 17:42         ` Andrew Cagney
2003-08-20 16:44           ` Daniel Jacobowitz
2003-07-31 21:00     ` Andrew Cagney

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