From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19435 invoked by alias); 27 Jul 2003 18:55:28 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 19428 invoked from network); 27 Jul 2003 18:55:27 -0000 Received: from unknown (HELO oberon.asicdesigners.com) (12.98.126.212) by sources.redhat.com with SMTP; 27 Jul 2003 18:55:27 -0000 Received: from oberon.asicdesigners.com (localhost.asicdesigners.com [127.0.0.1]) by oberon.asicdesigners.com (8.12.9/8.12.9) with ESMTP id h6RItI4w043771; Sun, 27 Jul 2003 11:55:19 -0700 (PDT) (envelope-from steve@oberon.asicdesigners.com) Received: (from steve@localhost) by oberon.asicdesigners.com (8.12.9/8.12.9/Submit) id h6RItIho043770; Sun, 27 Jul 2003 11:55:18 -0700 (PDT) Message-Id: <200307271855.h6RItIho043770@oberon.asicdesigners.com> From: steve@asicdesigners.com (Steve Watt) Date: Sun, 27 Jul 2003 18:55:00 -0000 In-Reply-To: Andrew Cagney "[patch rfc, 6.0?] only allow raw raw registers; Was: [patch rfc] Add NUM_REGS pseudo regs to MIPS" (Jul 27, 9:50) To: Andrew Cagney , gdb-patches@sources.redhat.com Subject: Re: [patch rfc, 6.0?] only allow raw raw registers; Was: [patch rfc] Add NUM_REGS pseudo regs to MIPS X-SW-Source: 2003-07/txt/msg00476.txt.bz2 On Jul 27, 9:50, Andrew Cagney wrote: } Subject: [patch rfc, 6.0?] only allow raw raw registers; Was: [patch rfc] } } Hello, } } The attached hopefully fixes the panic that SteveW was noticing with the } MIPS GNU/Linux target. It chops the legacy register cache (which the } MIPS uses) back so that it can no longer contain pseudo registers. } } Working through the build list, it has the potential of also affecting: } } h8300hms:gdbarch_dump: NUM_PSEUDO_REGS = 1 } i386-elf:gdbarch_dump: NUM_PSEUDO_REGS = 8 } m68hc11-elf:gdbarch_dump: NUM_PSEUDO_REGS = 37 } mips-elf:gdbarch_dump: NUM_PSEUDO_REGS = 90 } x86_64-linux-gnu:gdbarch_dump: NUM_PSEUDO_REGS = 8 } } (and sh64) } } but since everything is now using pseudo register read/write, instead of } fetch/store pseudo register (I deleted that), it should ho longer have } any affect. } } Hmm, if fetch/store pseudo is deleted all sorts of code can go .... } } Steve, does this fix your problem? Assuming it does, I'll also look to } commit this to the 6.0 branch. How about halfway? It fixes the abort, but leaves a weirdo in the output: (steve@mustang) 48> ./gdb /users/steve/tmp/t/hello.mips GNU gdb 2003-07-27-cvs Copyright 2003 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "--host=i686-pc-linux-gnu --target=mips-elf"... Setting up the environment for debugging gdb. .gdbinit:5: Error in sourced command file: Function "internal_error" not defined. (gdb) target sim Connected to the simulator. (gdb) load Loading section .text, size 0x150c vma 0xa0020000 Loading section .init, size 0x38 vma 0xa002150c Loading section .fini, size 0x28 vma 0xa0021544 Loading section .sdata, size 0x14 vma 0xa0021d20 Loading section .ctors, size 0x8 vma 0xa002156c Loading section .dtors, size 0x8 vma 0xa0021574 Loading section .rodata, size 0x2 vma 0xa002157c Loading section .eh_frame, size 0x4 vma 0xa0021580 Loading section .data, size 0x790 vma 0xa0021588 Loading section .jcr, size 0x4 vma 0xa0021d18 Start address 0xa0020004 Transfer rate: 59728 bits in <1 sec. (gdb) break _start Breakpoint 1 at 0xa0020004: file ../../../../combined/libgloss/mips/crt0.S, line 74. (gdb) run Starting program: /users/steve/tmp/t/hello.mips Breakpoint 1, _start () at ../../../../combined/libgloss/mips/crt0.S:74 74 li v0, STATUS_MASK Current language: auto; currently asm (gdb) info regs Undefined info command: "regs". Try "help info". (gdb) info regi zero at v0 v1 a0 a1 a2 a3 R90 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 t0 t1 t2 t3 t4 t5 t6 t7 R98 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 s0 s1 s2 s3 s4 s5 s6 s7 R106 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 t8 t9 k0 k1 gp sp s8 ra R114 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 sr lo hi bad cause pc 00400004 00000000 00000000 00000000 00000000 a0020004 fsr fir 00000000 00000000 (gdb) It's displaying stuff (and further runs appear correct), but the register number in the left column needs 90 subtracted. (Well, I'm sure there's a real fix, but...) So far, so good. -- Steve Watt KD6GGD PP-ASEL-IA Email at home: steve@watt.com Chelsio Communications http://www.chelsio.com/ work: steve@chelsio.com 510 N. Pastoria Ave Voice: +1 408 962 3627 Sunnyvale, CA, USA, 94085 Fax: +1 408 730 2580