Hello,

The attached hopefully fixes the panic that SteveW was noticing with the 
MIPS GNU/Linux target.   It chops the legacy register cache (which the 
MIPS uses) back so that it can no longer contain pseudo registers.

Working through the build list, it has the potential of also affecting:

h8300hms:gdbarch_dump: NUM_PSEUDO_REGS = 1
i386-elf:gdbarch_dump: NUM_PSEUDO_REGS = 8
m68hc11-elf:gdbarch_dump: NUM_PSEUDO_REGS = 37
mips-elf:gdbarch_dump: NUM_PSEUDO_REGS = 90
x86_64-linux-gnu:gdbarch_dump: NUM_PSEUDO_REGS = 8

(and sh64)

but since everything is now using pseudo register read/write, instead of 
fetch/store pseudo register (I deleted that), it should ho longer have 
any affect.

Hmm, if fetch/store pseudo is deleted all sorts of code can go ....

Steve, does this fix your problem?  Assuming it does, I'll also look to 
commit this to the 6.0 branch.

Andrew