[PATCH 04/12] gdb: Sync up x86-gcc-cpuid.h with cpuid.h from gcc 14 branch.

["Schimpe, Christina" <christina.schimpe@intel.com>]

This is required for a later commit which requires "bit_SHSTK".
---
 gdb/nat/x86-gcc-cpuid.h | 153 ++++++++++++++++++++++++++++++++--------
 1 file changed, 122 insertions(+), 31 deletions(-)

diff --git a/gdb/nat/x86-gcc-cpuid.h b/gdb/nat/x86-gcc-cpuid.h
index b0f2d239af3..a571eb8a734 100644
--- a/gdb/nat/x86-gcc-cpuid.h
+++ b/gdb/nat/x86-gcc-cpuid.h
@@ -1,5 +1,5 @@
 /*
- * Helper cpuid.h file copied from gcc-6.0.0.  Code in gdb should not
+ * Helper cpuid.h file copied from gcc-14-2-0.  Code in gdb should not
  * include this directly, but pull in x86-cpuid.h and use that func.
  */
 
@@ -55,7 +55,7 @@
 #define bit_SSE		(1 << 25)
 #define bit_SSE2	(1 << 26)
 
-/* Extended Features */
+/* Extended Features (%eax == 0x80000001) */
 /* %ecx */
 #define bit_LAHF_LM	(1 << 0)
 #define bit_ABM		(1 << 5)
@@ -68,29 +68,28 @@
 #define bit_MWAITX      (1 << 29)
 
 /* %edx */
-#define bit_AVX5124VNNIW (1 << 2)
-#define bit_AVX5124FMAPS (1 << 3)
 #define bit_MMXEXT	(1 << 22)
 #define bit_LM		(1 << 29)
 #define bit_3DNOWP	(1 << 30)
-#define bit_3DNOW	(1 << 31)
+#define bit_3DNOW	(1u << 31)
 
-/* %ebx.  */
+/* %ebx  */
 #define bit_CLZERO	(1 << 0)
+#define bit_WBNOINVD	(1 << 9)
 
-/* Extended Features (%eax == 7) */
+/* Extended Features Leaf (%eax == 7, %ecx == 0) */
 /* %ebx */
 #define bit_FSGSBASE	(1 << 0)
-#define bit_BMI	(1 << 3)
-#define bit_HLE	(1 << 4)
+#define bit_SGX		(1 << 2)
+#define bit_BMI		(1 << 3)
+#define bit_HLE		(1 << 4)
 #define bit_AVX2	(1 << 5)
 #define bit_BMI2	(1 << 8)
-#define bit_RTM	(1 << 11)
-#define bit_MPX	(1 << 14)
+#define bit_RTM		(1 << 11)
 #define bit_AVX512F	(1 << 16)
 #define bit_AVX512DQ	(1 << 17)
 #define bit_RDSEED	(1 << 18)
-#define bit_ADX	(1 << 19)
+#define bit_ADX		(1 << 19)
 #define bit_AVX512IFMA	(1 << 21)
 #define bit_CLFLUSHOPT	(1 << 23)
 #define bit_CLWB	(1 << 24)
@@ -99,23 +98,85 @@
 #define bit_AVX512CD	(1 << 28)
 #define bit_SHA		(1 << 29)
 #define bit_AVX512BW	(1 << 30)
-#define bit_AVX512VL	(1 << 31)
+#define bit_AVX512VL	(1u << 31)
 
 /* %ecx */
-#define bit_PREFETCHWT1	  (1 << 0)
+#define bit_PREFETCHWT1	(1 << 0)
 #define bit_AVX512VBMI	(1 << 1)
-#define bit_PKU	(1 << 3)
+#define bit_PKU		(1 << 3)
 #define bit_OSPKE	(1 << 4)
+#define bit_WAITPKG	(1 << 5)
+#define bit_AVX512VBMI2	(1 << 6)
+#define bit_SHSTK	(1 << 7)
+#define bit_GFNI	(1 << 8)
+#define bit_VAES	(1 << 9)
+#define bit_VPCLMULQDQ	(1 << 10)
+#define bit_AVX512VNNI	(1 << 11)
+#define bit_AVX512BITALG	(1 << 12)
+#define bit_AVX512VPOPCNTDQ	(1 << 14)
+#define bit_RDPID	(1 << 22)
+#define bit_KL		(1 << 23)
+#define bit_CLDEMOTE	(1 << 25)
+#define bit_MOVDIRI	(1 << 27)
+#define bit_MOVDIR64B	(1 << 28)
+#define bit_ENQCMD	(1 << 29)
 
-/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
-#define bit_BNDREGS     (1 << 3)
-#define bit_BNDCSR      (1 << 4)
+/* %edx */
+#define bit_AVX5124VNNIW	(1 << 2)
+#define bit_AVX5124FMAPS	(1 << 3)
+#define bit_UINTR	(1 << 5)
+#define bit_AVX512VP2INTERSECT	(1 << 8)
+#define bit_SERIALIZE	(1 << 14)
+#define bit_TSXLDTRK    (1 << 16)
+#define bit_PCONFIG	(1 << 18)
+#define bit_IBT         (1 << 20)
+#define bit_AMX_BF16    (1 << 22)
+#define bit_AVX512FP16	(1 << 23)
+#define bit_AMX_TILE    (1 << 24)
+#define bit_AMX_INT8    (1 << 25)
+
+/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */
+/* %eax */
+#define bit_SHA512	(1 << 0)
+#define bit_SM3		(1 << 1)
+#define bit_SM4		(1 << 2)
+#define bit_RAOINT      (1 << 3)
+#define bit_AVXVNNI     (1 << 4)
+#define bit_AVX512BF16  (1 << 5)
+#define bit_CMPCCXADD   (1 << 7)
+#define bit_AMX_COMPLEX (1 << 8)
+#define bit_AMX_FP16    (1 << 21)
+#define bit_HRESET      (1 << 22)
+#define bit_AVXIFMA     (1 << 23)
 
-/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
+/* %edx */
+#define bit_AVXVNNIINT8 (1 << 4)
+#define bit_AVXNECONVERT	(1 << 5)
+#define bit_AVXVNNIINT16	(1 << 10)
+#define bit_PREFETCHI	(1 << 14)
+#define bit_USER_MSR	(1 << 15)
+#define bit_AVX10	(1 << 19)
+#define bit_APX_F	(1 << 21)
+
+/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
 #define bit_XSAVEOPT	(1 << 0)
 #define bit_XSAVEC	(1 << 1)
 #define bit_XSAVES	(1 << 3)
 
+/* PT sub leaf (%eax == 0x14, %ecx == 0) */
+/* %ebx */
+#define bit_PTWRITE	(1 << 4)
+
+/* Keylocker leaf (%eax == 0x19) */
+/* %ebx */
+#define bit_AESKLE	( 1<<0 )
+#define bit_WIDEKL	( 1<<2 )
+
+/* AVX10 sub leaf (%eax == 0x24) */
+/* %ebx */
+#define bit_AVX10_256	(1 << 17)
+#define bit_AVX10_512	(1 << 18)
+
 /* Signatures for different CPU implementations as returned in uses
    of cpuid with level 0.  */
 #define signature_AMD_ebx	0x68747541
@@ -170,19 +231,40 @@
 #define signature_VORTEX_ecx	0x436f5320
 #define signature_VORTEX_edx	0x36387865
 
-#define __cpuid(level, a, b, c, d)			\
-  __asm__ ("cpuid\n\t"					\
-	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level))
+#define signature_SHANGHAI_ebx	0x68532020
+#define signature_SHANGHAI_ecx	0x20206961
+#define signature_SHANGHAI_edx	0x68676e61
 
-#define __cpuid_count(level, count, a, b, c, d)		\
-  __asm__ ("cpuid\n\t"					\
-	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level), "2" (count))
+#ifndef __x86_64__
+/* At least one cpu (Winchip 2) does not set %ebx and %ecx
+   for cpuid leaf 1. Forcibly zero the two registers before
+   calling cpuid as a precaution.  */
+#define __cpuid(level, a, b, c, d)					\
+  do {									\
+    if (__builtin_constant_p (level) && (level) != 1)			\
+      __asm__ __volatile__ ("cpuid\n\t"					\
+			    : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
+			    : "0" (level));				\
+    else								\
+      __asm__ __volatile__ ("cpuid\n\t"					\
+			    : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
+			    : "0" (level), "1" (0), "2" (0));		\
+  } while (0)
+#else
+#define __cpuid(level, a, b, c, d)					\
+  __asm__ __volatile__ ("cpuid\n\t"					\
+			: "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
+			: "0" (level))
+#endif
+
+#define __cpuid_count(level, count, a, b, c, d)				\
+  __asm__ __volatile__ ("cpuid\n\t"					\
+			: "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
+			: "0" (level), "2" (count))
 
 
 /* Return highest supported input value for cpuid instruction.  ext can
-   be either 0x0 or 0x8000000 to return highest supported value for
+   be either 0x0 or 0x80000000 to return highest supported value for
    basic or extended cpuid information.  Function returns 0 if cpuid
    is not supported or whatever cpuid returns in eax register.  If sig
    pointer is non-null, then first four bytes of the signature
@@ -225,7 +307,7 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 	   : "i" (0x00200000));
 #endif
 
-  if (!((__eax ^ __ebx) & 0x00200000))
+  if (__builtin_expect (!((__eax ^ __ebx) & 0x00200000), 0))
     return 0;
 #endif
 
@@ -249,8 +331,9 @@ __get_cpuid (unsigned int __leaf,
 	     unsigned int *__ecx, unsigned int *__edx)
 {
   unsigned int __ext = __leaf & 0x80000000;
+  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
 
-  if (__get_cpuid_max (__ext, 0) < __leaf)
+  if (__maxlevel == 0 || __maxlevel < __leaf)
     return 0;
 
   __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
@@ -265,12 +348,20 @@ __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
 		   unsigned int *__ecx, unsigned int *__edx)
 {
   unsigned int __ext = __leaf & 0x80000000;
+  unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
 
-  if (__get_cpuid_max (__ext, 0) < __leaf)
+  if (__builtin_expect (__maxlevel == 0, 0) || __maxlevel < __leaf)
     return 0;
 
   __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
   return 1;
 }
 
+static __inline void
+__cpuidex (int __cpuid_info[4], int __leaf, int __subleaf)
+{
+  __cpuid_count (__leaf, __subleaf, __cpuid_info[0], __cpuid_info[1],
+		 __cpuid_info[2], __cpuid_info[3]);
+}
+
 #endif /* GDB_NAT_X86_GCC_CPUID_H */
-- 
2.34.1

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928