* [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls
@ 2024-11-17 9:27 Dimitar Dimitrov
2024-11-17 9:27 ` [PATCH 2/2] sim: Add rv32e test cases Dimitar Dimitrov
2025-01-04 16:16 ` [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls Dimitar Dimitrov
0 siblings, 2 replies; 3+ messages in thread
From: Dimitar Dimitrov @ 2024-11-17 9:27 UTC (permalink / raw)
To: gdb-patches; +Cc: Dimitar Dimitrov
The I and E base ISA variants have incompatible ecall ABI. The system
call number for E ISA is passed in t0 register, whereas for I ISA it
is passed in a7 register.
Fix by checking the base ISA variant to choose which register to read
for the system call number. That requires a bit of refactoring to split
the I and E ISA base variants, since they are fundamentally different
per the specification [1].
With this fix I can run the GCC testsuite for RV32EC.
[1] The RISC-V Instruction Set Manual, volume I, version 2.1
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
sim/riscv/machs.c | 75 ++++++++++++++++---
sim/riscv/machs.h | 12 ++-
sim/riscv/model_list_e.def | 8 ++
.../{model_list.def => model_list_i.def} | 8 --
sim/riscv/riscv-sim.h | 5 ++
sim/riscv/sim-main.c | 6 +-
6 files changed, 93 insertions(+), 21 deletions(-)
create mode 100644 sim/riscv/model_list_e.def
rename sim/riscv/{model_list.def => model_list_i.def} (54%)
diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c
index 77ae000e7a5..034f7bfa598 100644
--- a/sim/riscv/machs.c
+++ b/sim/riscv/machs.c
@@ -49,10 +49,10 @@ static const SIM_MACH_IMP_PROPERTIES riscv_imp_properties =
static const SIM_MACH rv32i_mach;
-static const SIM_MODEL rv32_models[] =
+static const SIM_MODEL rv32i_models[] =
{
#define M(ext) { "RV32"#ext, &rv32i_mach, MODEL_RV32##ext, NULL, riscv_model_init },
-#include "model_list.def"
+#include "model_list_i.def"
#undef M
{ 0, NULL, 0, NULL, NULL, }
};
@@ -60,7 +60,25 @@ static const SIM_MODEL rv32_models[] =
static const SIM_MACH rv32i_mach =
{
"rv32i", "riscv:rv32", MACH_RV32I,
- 32, 32, &rv32_models[0], &riscv_imp_properties,
+ 32, 32, &rv32i_models[0], &riscv_imp_properties,
+ riscv_init_cpu,
+ riscv_prepare_run
+};
+
+static const SIM_MACH rv32e_mach;
+
+static const SIM_MODEL rv32e_models[] =
+{
+#define M(ext) { "RV32"#ext, &rv32e_mach, MODEL_RV32##ext, NULL, riscv_model_init },
+#include "model_list_e.def"
+#undef M
+ { 0, NULL, 0, NULL, NULL, }
+};
+
+static const SIM_MACH rv32e_mach =
+{
+ "rv32e", "riscv:rv32", MACH_RV32E,
+ 32, 32, &rv32e_models[0], &riscv_imp_properties,
riscv_init_cpu,
riscv_prepare_run
};
@@ -71,10 +89,10 @@ static const SIM_MACH rv32i_mach =
static const SIM_MACH rv64i_mach;
-static const SIM_MODEL rv64_models[] =
+static const SIM_MODEL rv64i_models[] =
{
#define M(ext) { "RV64"#ext, &rv64i_mach, MODEL_RV64##ext, NULL, riscv_model_init },
-#include "model_list.def"
+#include "model_list_i.def"
#undef M
{ 0, NULL, 0, NULL, NULL, }
};
@@ -82,7 +100,25 @@ static const SIM_MODEL rv64_models[] =
static const SIM_MACH rv64i_mach =
{
"rv64i", "riscv:rv64", MACH_RV64I,
- 64, 64, &rv64_models[0], &riscv_imp_properties,
+ 64, 64, &rv64i_models[0], &riscv_imp_properties,
+ riscv_init_cpu,
+ riscv_prepare_run
+};
+
+static const SIM_MACH rv64e_mach;
+
+static const SIM_MODEL rv64e_models[] =
+{
+#define M(ext) { "RV64"#ext, &rv64e_mach, MODEL_RV64##ext, NULL, riscv_model_init },
+#include "model_list_e.def"
+#undef M
+ { 0, NULL, 0, NULL, NULL, }
+};
+
+static const SIM_MACH rv64e_mach =
+{
+ "rv64e", "riscv:rv64", MACH_RV64E,
+ 64, 64, &rv64e_models[0], &riscv_imp_properties,
riscv_init_cpu,
riscv_prepare_run
};
@@ -93,10 +129,10 @@ static const SIM_MACH rv64i_mach =
static const SIM_MACH rv128i_mach;
-static const SIM_MODEL rv128_models[] =
+static const SIM_MODEL rv128i_models[] =
{
#define M(ext) { "RV128"#ext, &rv128i_mach, MODEL_RV128##ext, NULL, riscv_model_init },
-#include "model_list.def"
+#include "model_list_i.def"
#undef M
{ 0, NULL, 0, NULL, NULL, }
};
@@ -104,7 +140,25 @@ static const SIM_MODEL rv128_models[] =
static const SIM_MACH rv128i_mach =
{
"rv128i", "riscv:rv128", MACH_RV128I,
- 128, 128, &rv128_models[0], &riscv_imp_properties,
+ 128, 128, &rv128i_models[0], &riscv_imp_properties,
+ riscv_init_cpu,
+ riscv_prepare_run
+};
+
+static const SIM_MACH rv128e_mach;
+
+static const SIM_MODEL rv128e_models[] =
+{
+#define M(ext) { "RV128"#ext, &rv128e_mach, MODEL_RV128##ext, NULL, riscv_model_init },
+#include "model_list_e.def"
+#undef M
+ { 0, NULL, 0, NULL, NULL, }
+};
+
+static const SIM_MACH rv128e_mach =
+{
+ "rv128e", "riscv:rv128", MACH_RV128E,
+ 128, 128, &rv128e_models[0], &riscv_imp_properties,
riscv_init_cpu,
riscv_prepare_run
};
@@ -116,12 +170,15 @@ const SIM_MACH * const riscv_sim_machs[] =
{
#if WITH_TARGET_WORD_BITSIZE >= 128
&rv128i_mach,
+ &rv128e_mach,
#endif
#if WITH_TARGET_WORD_BITSIZE >= 64
&rv64i_mach,
+ &rv64e_mach,
#endif
#if WITH_TARGET_WORD_BITSIZE >= 32
&rv32i_mach,
+ &rv32e_mach,
#endif
NULL
};
diff --git a/sim/riscv/machs.h b/sim/riscv/machs.h
index 0a24c16f33a..8c18a348885 100644
--- a/sim/riscv/machs.h
+++ b/sim/riscv/machs.h
@@ -23,13 +23,16 @@
typedef enum model_type {
#define M(ext) MODEL_RV32##ext,
-#include "model_list.def"
+#include "model_list_i.def"
+#include "model_list_e.def"
#undef M
#define M(ext) MODEL_RV64##ext,
-#include "model_list.def"
+#include "model_list_i.def"
+#include "model_list_e.def"
#undef M
#define M(ext) MODEL_RV128##ext,
-#include "model_list.def"
+#include "model_list_i.def"
+#include "model_list_e.def"
#undef M
MODEL_MAX
} MODEL_TYPE;
@@ -37,8 +40,11 @@ typedef enum model_type {
typedef enum mach_attr {
MACH_BASE,
MACH_RV32I,
+ MACH_RV32E,
MACH_RV64I,
+ MACH_RV64E,
MACH_RV128I,
+ MACH_RV128E,
MACH_MAX
} MACH_ATTR;
diff --git a/sim/riscv/model_list_e.def b/sim/riscv/model_list_e.def
new file mode 100644
index 00000000000..954467d2d0a
--- /dev/null
+++ b/sim/riscv/model_list_e.def
@@ -0,0 +1,8 @@
+M(E)
+M(EM)
+M(EMA)
+M(EA)
+M(EC)
+M(EMC)
+M(EMAC)
+M(EAC)
diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list_i.def
similarity index 54%
rename from sim/riscv/model_list.def
rename to sim/riscv/model_list_i.def
index b83557e5539..49fd26a64db 100644
--- a/sim/riscv/model_list.def
+++ b/sim/riscv/model_list_i.def
@@ -8,11 +8,3 @@ M(IC)
M(IMC)
M(IMAC)
M(IAC)
-M(E)
-M(EM)
-M(EMA)
-M(EA)
-M(EC)
-M(EMC)
-M(EMAC)
-M(EAC)
diff --git a/sim/riscv/riscv-sim.h b/sim/riscv/riscv-sim.h
index 345e6835b1d..b017a93e37b 100644
--- a/sim/riscv/riscv-sim.h
+++ b/sim/riscv/riscv-sim.h
@@ -74,5 +74,10 @@ extern void initialize_env (SIM_DESC, const char * const *argv,
#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
+#define RISCV_ISA_IS_E(cpu) \
+ ({ int mach_num = MACH_NUM (CPU_MACH (cpu)); \
+ (mach_num == MACH_RV32E \
+ || mach_num == MACH_RV64E \
+ || mach_num == MACH_RV128E) ? true : false; })
#endif
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 378e6f1dc69..b228acd1ef9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -36,6 +36,7 @@
#include "sim/sim-riscv.h"
#include "riscv-sim.h"
+#include "machs.h"
\f
#define TRACE_REG(cpu, reg) \
TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \
@@ -168,6 +169,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
unsigned_word tmp;
+ unsigned_word syscall_func;
sim_cia pc = riscv_cpu->pc + 4;
TRACE_EXTRACT (cpu,
@@ -627,7 +629,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
break;
case MATCH_ECALL:
TRACE_INSN (cpu, "ecall;");
- riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
+ /* Syscall function number. */
+ syscall_func = RISCV_ISA_IS_E (cpu) ? riscv_cpu->t0 : riscv_cpu->a7;
+ riscv_cpu->a0 = sim_syscall (cpu, syscall_func, riscv_cpu->a0,
riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
break;
default:
--
2.47.0
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 2/2] sim: Add rv32e test cases
2024-11-17 9:27 [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls Dimitar Dimitrov
@ 2024-11-17 9:27 ` Dimitar Dimitrov
2025-01-04 16:16 ` [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls Dimitar Dimitrov
1 sibling, 0 replies; 3+ messages in thread
From: Dimitar Dimitrov @ 2024-11-17 9:27 UTC (permalink / raw)
To: gdb-patches; +Cc: Dimitar Dimitrov
Split the testutils assembler header into two - for I and for E
ISA variants. This is necessary because the system call ID is passed in
different registers.
Add a simple pass-rv32e.s test mimicking the pass.s for the I ISA
variant.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
sim/testsuite/riscv/c-ext.s | 2 +-
sim/testsuite/riscv/jalr.s | 8 ++-
sim/testsuite/riscv/m-ext.s | 8 ++-
sim/testsuite/riscv/pass-rv32e.s | 10 ++++
sim/testsuite/riscv/pass.s | 8 ++-
sim/testsuite/riscv/testutils-e.inc | 58 +++++++++++++++++++
.../riscv/{testutils.inc => testutils-i.inc} | 0
7 files changed, 90 insertions(+), 4 deletions(-)
create mode 100644 sim/testsuite/riscv/pass-rv32e.s
create mode 100644 sim/testsuite/riscv/testutils-e.inc
rename sim/testsuite/riscv/{testutils.inc => testutils-i.inc} (100%)
diff --git a/sim/testsuite/riscv/c-ext.s b/sim/testsuite/riscv/c-ext.s
index ad6e7b239f2..3836621fb5c 100644
--- a/sim/testsuite/riscv/c-ext.s
+++ b/sim/testsuite/riscv/c-ext.s
@@ -7,7 +7,7 @@
# as(riscv32): -march=rv32ic
# as(riscv64): -march=rv64ic
-.include "testutils.inc"
+.include "testutils-i.inc"
.data
.align 4
diff --git a/sim/testsuite/riscv/jalr.s b/sim/testsuite/riscv/jalr.s
index 294f48564d8..211cfb32300 100644
--- a/sim/testsuite/riscv/jalr.s
+++ b/sim/testsuite/riscv/jalr.s
@@ -1,7 +1,13 @@
# Basic jalr tests.
# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IC
+# sim(riscv64): --model RV64IC
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32ic
+# as(riscv64): -march=rv64ic
-.include "testutils.inc"
+.include "testutils-i.inc"
start
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
index 4247156bea4..cdefcc7b63a 100644
--- a/sim/testsuite/riscv/m-ext.s
+++ b/sim/testsuite/riscv/m-ext.s
@@ -1,7 +1,13 @@
# Check that the RV32M instructions run without any faults.
# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IC
+# sim(riscv64): --model RV64IC
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32ic
+# as(riscv64): -march=rv64ic
-.include "testutils.inc"
+.include "testutils-i.inc"
start
diff --git a/sim/testsuite/riscv/pass-rv32e.s b/sim/testsuite/riscv/pass-rv32e.s
new file mode 100644
index 00000000000..18ef08ae2b3
--- /dev/null
+++ b/sim/testsuite/riscv/pass-rv32e.s
@@ -0,0 +1,10 @@
+# check that the sim doesn't die immediately.
+# mach: riscv32
+# sim(riscv32): --model RV32EC
+# ld(riscv32): -m elf32lriscv
+# as(riscv32): -march=rv32ec
+
+.include "testutils-e.inc"
+
+ start
+ pass
diff --git a/sim/testsuite/riscv/pass.s b/sim/testsuite/riscv/pass.s
index a188b83a026..41643d521ee 100644
--- a/sim/testsuite/riscv/pass.s
+++ b/sim/testsuite/riscv/pass.s
@@ -1,7 +1,13 @@
# check that the sim doesn't die immediately.
# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IC
+# sim(riscv64): --model RV64IC
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32ic
+# as(riscv64): -march=rv64ic
-.include "testutils.inc"
+.include "testutils-i.inc"
start
pass
diff --git a/sim/testsuite/riscv/testutils-e.inc b/sim/testsuite/riscv/testutils-e.inc
new file mode 100644
index 00000000000..b0df340dc89
--- /dev/null
+++ b/sim/testsuite/riscv/testutils-e.inc
@@ -0,0 +1,58 @@
+# MACRO: exit
+ .macro exit nr
+ li a0, \nr
+ # The exit utility function.
+ li t0, 93;
+ # Trigger OS trap.
+ ecall;
+ .endm
+
+# MACRO: pass
+# Write 'pass' to stdout and quit.
+ .macro pass
+ # syscall write().
+ li t0, 64;
+ # Use stdout.
+ li a0, 1;
+ # Point to the string.
+ lla a1, 1f;
+ # Number of bytes to write.
+ li a2, 5;
+ # Trigger OS trap.
+ ecall;
+ exit 0;
+ .pushsection .data
+ 1: .asciz "pass\n"
+ .popsection
+ .endm
+
+# MACRO: fail
+# Write 'fail' to stdout and quit.
+ .macro fail
+ # syscall write().
+ li t0, 64;
+ # Use stdout.
+ li a0, 1;
+ # Point to the string.
+ la a1, 1f;
+ # Number of bytes to write.
+ li a2, 5;
+ # Trigger OS trap.
+ ecall;
+ exit 0;
+ .pushsection .data
+ 1: .asciz "fail\n"
+ .popsection
+ .endm
+
+# MACRO: start
+# All assembler tests should start with a call to "start".
+ .macro start
+ .text
+.global _start
+_start:
+ .option push
+ .option norelax
+ lla gp, __global_pointer$
+ .option pop
+ .endm
diff --git a/sim/testsuite/riscv/testutils.inc b/sim/testsuite/riscv/testutils-i.inc
similarity index 100%
rename from sim/testsuite/riscv/testutils.inc
rename to sim/testsuite/riscv/testutils-i.inc
--
2.47.0
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls
2024-11-17 9:27 [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls Dimitar Dimitrov
2024-11-17 9:27 ` [PATCH 2/2] sim: Add rv32e test cases Dimitar Dimitrov
@ 2025-01-04 16:16 ` Dimitar Dimitrov
1 sibling, 0 replies; 3+ messages in thread
From: Dimitar Dimitrov @ 2025-01-04 16:16 UTC (permalink / raw)
To: gdb-patches
On Sun, Nov 17, 2024 at 11:27:36AM +0200, Dimitar Dimitrov wrote:
> The I and E base ISA variants have incompatible ecall ABI. The system
> call number for E ISA is passed in t0 register, whereas for I ISA it
> is passed in a7 register.
>
> Fix by checking the base ISA variant to choose which register to read
> for the system call number. That requires a bit of refactoring to split
> the I and E ISA base variants, since they are fundamentally different
> per the specification [1].
>
> With this fix I can run the GCC testsuite for RV32EC.
>
> [1] The RISC-V Instruction Set Manual, volume I, version 2.1
>
> Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
> ---
> sim/riscv/machs.c | 75 ++++++++++++++++---
> sim/riscv/machs.h | 12 ++-
> sim/riscv/model_list_e.def | 8 ++
> .../{model_list.def => model_list_i.def} | 8 --
> sim/riscv/riscv-sim.h | 5 ++
> sim/riscv/sim-main.c | 6 +-
> 6 files changed, 93 insertions(+), 21 deletions(-)
> create mode 100644 sim/riscv/model_list_e.def
> rename sim/riscv/{model_list.def => model_list_i.def} (54%)
>
Gentle ping.
Regards,
Dimitar
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