Re: [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls

[Dimitar Dimitrov <dimitar@dinux.eu>]

On Sun, Nov 17, 2024 at 11:27:36AM +0200, Dimitar Dimitrov wrote:
> The I and E base ISA variants have incompatible ecall ABI.  The system
> call number for E ISA is passed in t0 register, whereas for I ISA it
> is passed in a7 register.
> 
> Fix by checking the base ISA variant to choose which register to read
> for the system call number.  That requires a bit of refactoring to split
> the I and E ISA base variants, since they are fundamentally different
> per the specification [1].
> 
> With this fix I can run the GCC testsuite for RV32EC.
> 
> [1] The RISC-V Instruction Set Manual, volume I, version 2.1
> 
> Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
> ---
>  sim/riscv/machs.c                             | 75 ++++++++++++++++---
>  sim/riscv/machs.h                             | 12 ++-
>  sim/riscv/model_list_e.def                    |  8 ++
>  .../{model_list.def => model_list_i.def}      |  8 --
>  sim/riscv/riscv-sim.h                         |  5 ++
>  sim/riscv/sim-main.c                          |  6 +-
>  6 files changed, 93 insertions(+), 21 deletions(-)
>  create mode 100644 sim/riscv/model_list_e.def
>  rename sim/riscv/{model_list.def => model_list_i.def} (54%)
> 

Gentle ping.

Regards,
Dimitar