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bh=MXAw6vYr8dPwKah0kFNJJCUEq6e6HPlfKx26nUnCIMU=; b=FF2z2aoNeQmvBtTHENvwSOsfPQ cyslUI3e4viW4tjHdl7N9hq0FEtWuTG5TT4ZAqwh+bvCm02wZ5dL5ggP5Omd2IoFdoUiLx1oLBWhQ 0h4xGROHA3hn8JlzDCLHqfEAo+0TerxqphF1wRg/RSRMUUZ3fme7iXBvLhF/I/Vy6oR5bdyKjngrx GbpvuSbMBLWK1X6/22TDQgHgFr1B++jbQN0cAvR++7HobvE5Aob+RBNdIT1fJfFf7C4B8sfaLmFl5 5oJIbBEekGbKpuU2cn5FcvsMqc3Ka+Y/n63mdNka0xIy4TtVVmsT48feI5lFjjqXL0xdvieD01tS7 y2xuuTDw==; Received: from 95-42-20-142.ip.btc-net.bg ([95.42.20.142]:52316 helo=localhost) by server28.superhosting.bg with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1tU6pJ-00D6pS-35 for gdb-patches@sourceware.org; Sat, 04 Jan 2025 18:16:40 +0200 Date: Sat, 4 Jan 2025 18:16:37 +0200 From: Dimitar Dimitrov To: gdb-patches@sourceware.org Subject: Re: [PATCH 1/2] sim: Fix argument handling for RISC-V E syscalls Message-ID: References: <20241117092738.449206-1-dimitar@dinux.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241117092738.449206-1-dimitar@dinux.eu> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server28.superhosting.bg X-AntiAbuse: Original Domain - sourceware.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - dinux.eu X-Get-Message-Sender-Via: server28.superhosting.bg: authenticated_id: dimitar@dinux.eu X-Authenticated-Sender: server28.superhosting.bg: dimitar@dinux.eu X-Source: X-Source-Args: X-Source-Dir: X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On Sun, Nov 17, 2024 at 11:27:36AM +0200, Dimitar Dimitrov wrote: > The I and E base ISA variants have incompatible ecall ABI. The system > call number for E ISA is passed in t0 register, whereas for I ISA it > is passed in a7 register. > > Fix by checking the base ISA variant to choose which register to read > for the system call number. That requires a bit of refactoring to split > the I and E ISA base variants, since they are fundamentally different > per the specification [1]. > > With this fix I can run the GCC testsuite for RV32EC. > > [1] The RISC-V Instruction Set Manual, volume I, version 2.1 > > Signed-off-by: Dimitar Dimitrov > --- > sim/riscv/machs.c | 75 ++++++++++++++++--- > sim/riscv/machs.h | 12 ++- > sim/riscv/model_list_e.def | 8 ++ > .../{model_list.def => model_list_i.def} | 8 -- > sim/riscv/riscv-sim.h | 5 ++ > sim/riscv/sim-main.c | 6 +- > 6 files changed, 93 insertions(+), 21 deletions(-) > create mode 100644 sim/riscv/model_list_e.def > rename sim/riscv/{model_list.def => model_list_i.def} (54%) > Gentle ping. Regards, Dimitar