* [patch ping2] Simulator Supports for MIPS32 DSP ASE
@ 2005-09-07 23:10 Chao-ying Fu
2005-09-10 3:56 ` Daniel Jacobowitz
0 siblings, 1 reply; 18+ messages in thread
From: Chao-ying Fu @ 2005-09-07 23:10 UTC (permalink / raw)
To: gdb-patches, Daniel Jacobowitz, echristo
Hello,
I posted this patch on Aug 12. Could anyone review it?
http://sources.redhat.com/ml/gdb-patches/2005-08/msg00147.html
Thanks a lot!
Regards,
Chao-ying
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-07 23:10 [patch ping2] Simulator Supports for MIPS32 DSP ASE Chao-ying Fu
@ 2005-09-10 3:56 ` Daniel Jacobowitz
2005-09-12 11:22 ` Nigel Stephens
2005-09-14 23:10 ` Chao-ying Fu
0 siblings, 2 replies; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-09-10 3:56 UTC (permalink / raw)
To: Chao-ying Fu; +Cc: gdb-patches, echristo
On Wed, Sep 07, 2005 at 04:08:36PM -0700, Chao-ying Fu wrote:
> Hello,
>
> I posted this patch on Aug 12. Could anyone review it?
> http://sources.redhat.com/ml/gdb-patches/2005-08/msg00147.html
>
> Thanks a lot!
I just can't review this patch; I don't know enough about the simulator
framework or igen. Is there anyone out there who feels capable? If
so, could you take a look, please?
The only comment I have is that a number of files say:
# Copyright (C) 2005 MIPS Technologies, Inc.
# All rights reserved.
I presume you intended to assign this to the FSF. If so, please fix
that notice.
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-10 3:56 ` Daniel Jacobowitz
@ 2005-09-12 11:22 ` Nigel Stephens
2005-09-12 12:53 ` Daniel Jacobowitz
2005-09-14 23:10 ` Chao-ying Fu
1 sibling, 1 reply; 18+ messages in thread
From: Nigel Stephens @ 2005-09-12 11:22 UTC (permalink / raw)
To: Daniel Jacobowitz; +Cc: Chao-ying Fu, gdb-patches, echristo
Daniel Jacobowitz wrote:
> The only comment I have is that a number of files say:
>
># Copyright (C) 2005 MIPS Technologies, Inc.
># All rights reserved.
>
>I presume you intended to assign this to the FSF. If so, please fix
>that notice.
>
>
>
Hi Daniel
We intend to handle the new files in the same way as many other gdb &
simulator contributions, i.e. MIPS retains the copyright, but releases
the code under GPL. For example see sim/arm/armemu.c or
gdb/rdi-share/ardi.c. Is there a problem with that?
Nigel
--
Nigel Stephens Mailto:nigel@mips.com
_ _ ____ ___ MIPS Technologies Phone.: +44 1223 706200
|\ /|||___)(___ The Fruit Farm Direct: +44 1223 706207
| \/ ||| ____) Ely Road, Chittering Fax...: +44 1223 706250
TECHNOLOGIES UK Cambridge CB5 9PH Cell..: +44 7976 686470
England http://www.mips.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-12 11:22 ` Nigel Stephens
@ 2005-09-12 12:53 ` Daniel Jacobowitz
[not found] ` <4325846F.5090809@mips.com>
0 siblings, 1 reply; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-09-12 12:53 UTC (permalink / raw)
To: Nigel Stephens; +Cc: Chao-ying Fu, gdb-patches, echristo
On Mon, Sep 12, 2005 at 12:21:05PM +0100, Nigel Stephens wrote:
>
>
> Daniel Jacobowitz wrote:
>
> >The only comment I have is that a number of files say:
> >
> ># Copyright (C) 2005 MIPS Technologies, Inc.
> ># All rights reserved.
> >
> >I presume you intended to assign this to the FSF. If so, please fix
> >that notice.
> >
> >
> >
>
> Hi Daniel
>
> We intend to handle the new files in the same way as many other gdb &
> simulator contributions, i.e. MIPS retains the copyright, but releases
> the code under GPL. For example see sim/arm/armemu.c or
> gdb/rdi-share/ardi.c. Is there a problem with that?
I'm not entirely current on these issues.
Apparently this is historically acceptable for the simulator. Yuck.
Andrew did some heroic work to improve the situation:
http://www.cygwin.com/ml/gdb/2002-09/msg00135.html
but I don't remember seeing any major changes since then.
In any case, you're adding new files to a directory in which everything
is copyright FSF. That doesn't seem like a good choice. The only new
files are tests, right?
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
[not found] ` <4325846F.5090809@mips.com>
@ 2005-09-12 13:43 ` Daniel Jacobowitz
2005-10-10 23:47 ` Daniel Jacobowitz
1 sibling, 0 replies; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-09-12 13:43 UTC (permalink / raw)
To: Nigel Stephens; +Cc: Chao-ying Fu, gdb-patches, echristo
On Mon, Sep 12, 2005 at 02:36:47PM +0100, Nigel Stephens wrote:
> It does seem to be accepted that the individual machine-specific
> directories will continue to contain code with "assorted" copyrights.
> Maybe this was felt to be necessary to encourage CPU manufacturers to
> contribute code which might have been derived from their own proprietary
> simulators, and who therefore wanted to retain copyright in order to
> protect their tools from malicious claims.
I think it's more a matter of inertia. We already had simulators not
copyright the FSF.
> >In any case, you're adding new files to a directory in which everything
> >is copyright FSF. That doesn't seem like a good choice. The only new
> >files are tests, right?
> >
> >
>
> There is the new file dsp.igen, which implements the DSP ASE
> instructions, and that is quite a significant new piece of code.
I see, I missed the new files, since they were attached rather than
part of the diff.
Most of the MIPS simulator is (C) FSF. But four files have assorted
other copyright status, and a number of major files have no listed
copyright status at all. So adding a couple files copyright MIPS is
not a big deal.
Objection withdrawn. If we need to revisit the license terms later, we
know where to find you :-)
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-10 3:56 ` Daniel Jacobowitz
2005-09-12 11:22 ` Nigel Stephens
@ 2005-09-14 23:10 ` Chao-ying Fu
2005-09-14 23:38 ` Eric Christopher
1 sibling, 1 reply; 18+ messages in thread
From: Chao-ying Fu @ 2005-09-14 23:10 UTC (permalink / raw)
To: Daniel Jacobowitz; +Cc: Thekkath, Radhika, echristo, gdb-patches
Hi Daniel,
It seems that no one will review this patch. Do you have any suggestion
for this situation? Could I just check in the patch?
Thanks!
Regards,
Chao-ying
----- Original Message -----
From: "Daniel Jacobowitz" <drow@false.org>
To: "Chao-ying Fu" <fu@mips.com>
Cc: <gdb-patches@sourceware.org>; <echristo@apple.com>
Sent: Friday, September 09, 2005 8:56 PM
Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
> On Wed, Sep 07, 2005 at 04:08:36PM -0700, Chao-ying Fu wrote:
> > Hello,
> >
> > I posted this patch on Aug 12. Could anyone review it?
> > http://sources.redhat.com/ml/gdb-patches/2005-08/msg00147.html
> >
> > Thanks a lot!
>
> I just can't review this patch; I don't know enough about the simulator
> framework or igen. Is there anyone out there who feels capable? If
> so, could you take a look, please?
>
> The only comment I have is that a number of files say:
> # Copyright (C) 2005 MIPS Technologies, Inc.
> # All rights reserved.
>
> I presume you intended to assign this to the FSF. If so, please fix
> that notice.
>
> --
> Daniel Jacobowitz
> CodeSourcery, LLC
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-14 23:10 ` Chao-ying Fu
@ 2005-09-14 23:38 ` Eric Christopher
2005-09-17 20:45 ` Daniel Jacobowitz
0 siblings, 1 reply; 18+ messages in thread
From: Eric Christopher @ 2005-09-14 23:38 UTC (permalink / raw)
To: Chao-ying Fu; +Cc: Daniel Jacobowitz, Thekkath, Radhika, gdb-patches
On Sep 14, 2005, at 4:08 PM, Chao-ying Fu wrote:
> Hi Daniel,
>
> It seems that no one will review this patch. Do you have any
> suggestion
> for this situation? Could I just check in the patch?
> Thanks!
>>
>> I just can't review this patch; I don't know enough about the
>> simulator
>> framework or igen. Is there anyone out there who feels capable? If
>> so, could you take a look, please?
I feel ok with reviewing it, I've just not had time yet. It's a lot
of code.
I'll get to it this weekend if no one else has.
-eric
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-14 23:38 ` Eric Christopher
@ 2005-09-17 20:45 ` Daniel Jacobowitz
2005-09-23 22:21 ` Chao-ying Fu
0 siblings, 1 reply; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-09-17 20:45 UTC (permalink / raw)
To: Eric Christopher; +Cc: Chao-ying Fu, Thekkath, Radhika, gdb-patches
On Wed, Sep 14, 2005 at 04:37:09PM -0700, Eric Christopher wrote:
>
> On Sep 14, 2005, at 4:08 PM, Chao-ying Fu wrote:
>
> >Hi Daniel,
> >
> > It seems that no one will review this patch. Do you have any
> >suggestion
> >for this situation? Could I just check in the patch?
> > Thanks!
> >>
> >>I just can't review this patch; I don't know enough about the
> >>simulator
> >>framework or igen. Is there anyone out there who feels capable? If
> >>so, could you take a look, please?
>
> I feel ok with reviewing it, I've just not had time yet. It's a lot
> of code.
>
> I'll get to it this weekend if no one else has.
No one else has, so I'll leave this in Eric's hands.
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-17 20:45 ` Daniel Jacobowitz
@ 2005-09-23 22:21 ` Chao-ying Fu
2005-09-23 22:23 ` Eric Christopher
0 siblings, 1 reply; 18+ messages in thread
From: Chao-ying Fu @ 2005-09-23 22:21 UTC (permalink / raw)
To: Eric Christopher; +Cc: Daniel Jacobowitz, Thekkath, Radhika, gdb-patches
Re: [patch ping2] Simulator Supports for MIPS32 DSP ASEHi Eric,
Any status update for the MIPS32 DSP simulator patch? Thanks!
Regards,
Chao-ying
----- Original Message -----
From: Daniel Jacobowitz
To: Eric Christopher
Cc: Fu, Chao-Ying ; Thekkath, Radhika ; gdb-patches@sourceware.org
Sent: Saturday, September 17, 2005 1:44 PM
Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
On Wed, Sep 14, 2005 at 04:37:09PM -0700, Eric Christopher wrote:
>
> On Sep 14, 2005, at 4:08 PM, Chao-ying Fu wrote:
>
> >Hi Daniel,
> >
> > It seems that no one will review this patch. Do you have any
> >suggestion
> >for this situation? Could I just check in the patch?
> > Thanks!
> >>
> >>I just can't review this patch; I don't know enough about the
> >>simulator
> >>framework or igen. Is there anyone out there who feels capable? If
> >>so, could you take a look, please?
>
> I feel ok with reviewing it, I've just not had time yet. It's a lot
> of code.
>
> I'll get to it this weekend if no one else has.
No one else has, so I'll leave this in Eric's hands.
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-09-23 22:21 ` Chao-ying Fu
@ 2005-09-23 22:23 ` Eric Christopher
0 siblings, 0 replies; 18+ messages in thread
From: Eric Christopher @ 2005-09-23 22:23 UTC (permalink / raw)
To: Chao-ying Fu; +Cc: Daniel Jacobowitz, Thekkath, Radhika, gdb-patches
On Sep 23, 2005, at 3:20 PM, Chao-ying Fu wrote:
> Re: [patch ping2] Simulator Supports for MIPS32 DSP ASEHi Eric,
>
> Any status update for the MIPS32 DSP simulator patch? Thanks!
>
I didn't get to it over the weekend obviously. It is still sitting in
my queue and I haven't forgotten it.
Soon. :)
-eric
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
[not found] ` <4325846F.5090809@mips.com>
2005-09-12 13:43 ` Daniel Jacobowitz
@ 2005-10-10 23:47 ` Daniel Jacobowitz
2005-10-11 8:37 ` Nigel Stephens
2005-10-11 22:07 ` Eric Christopher
1 sibling, 2 replies; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-10-10 23:47 UTC (permalink / raw)
To: Nigel Stephens; +Cc: Chao-ying Fu, gdb-patches, echristo
On Mon, Sep 12, 2005 at 02:36:47PM +0100, Nigel Stephens wrote:
> It does seem to be accepted that the individual machine-specific
> directories will continue to contain code with "assorted" copyrights.
> Maybe this was felt to be necessary to encourage CPU manufacturers to
> contribute code which might have been derived from their own proprietary
> simulators, and who therefore wanted to retain copyright in order to
> protect their tools from malicious claims.
Andrew has corrected me off-list: new, non-FSF contributions are not
acceptable. I entirely support that position. Is this going to be a
problem for MIPS?
The possible explanation that you provide does not seem credible to me,
but I'm not qualified to discuss it; we can refer any issues to the
FSF's counsel.
[Meanwhile, Eric, when this is settled I intend to approve the code
changes; if you feel like reviewing it after the fact, I'm sure MIPS
will be able to correct any problems.]
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-10-10 23:47 ` Daniel Jacobowitz
@ 2005-10-11 8:37 ` Nigel Stephens
2005-10-11 21:59 ` Chao-ying Fu
2005-10-11 22:07 ` Eric Christopher
1 sibling, 1 reply; 18+ messages in thread
From: Nigel Stephens @ 2005-10-11 8:37 UTC (permalink / raw)
To: Daniel Jacobowitz; +Cc: Chao-ying Fu, gdb-patches, echristo
Daniel Jacobowitz wrote:
>Andrew has corrected me off-list: new, non-FSF contributions are not
>acceptable. I entirely support that position. Is this going to be a
>problem for MIPS?
>
>
OK, we agree to assign copyright of these new files to the FSF. We'll
resubmit the patch with updated headers.
Nigel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-10-11 8:37 ` Nigel Stephens
@ 2005-10-11 21:59 ` Chao-ying Fu
0 siblings, 0 replies; 18+ messages in thread
From: Chao-ying Fu @ 2005-10-11 21:59 UTC (permalink / raw)
To: Nigel Stephens, Daniel Jacobowitz
Cc: Thekkath, Radhika, echristo, gdb-patches
[-- Attachment #1: Type: text/plain, Size: 2783 bytes --]
Hi,
Here is the revised patch for MIPS32 DSP ASE. We changed
the copyright to FSF for our new files. Tested with two
configurations. No new regressions. Is it ok to commit? Thanks!
Regards,
Chao-ying
1. --target=mipsisa32-elf
Test Run By fu on Tue Oct 11 14:02:10 2005
Target is mipsisa32-unknown-elf
Host is i686-pc-linux-gnu
=== sim Summary ===
# of expected passes 22
2. --target=mipsisa64-elf
Test Run By fu on Tue Oct 11 14:23:31 2005
Target is mipsisa64-unknown-elf
Host is i686-pc-linux-gnu
=== sim Summary ===
# of expected passes 45
# of unexpected failures 1
sim/mips/ChangeLog
2005-10-11 Chao-ying Fu <fu@mips.com>
* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove *mips32, *mips32r2, *mips64,
*mips64r2, because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
sim/testsuite/sim/mips/ChangeLog
2005-10-11 Chao-ying Fu <fu@mips.com>
* basic.exp: Run the dsp test.
* utils-dsp.inc: New file.
* mips32-dsp.s: New test.
----- Original Message -----
From: "Nigel Stephens" <nigel@mips.com>
To: "Daniel Jacobowitz" <drow@false.org>
Cc: "Chao-ying Fu" <fu@mips.com>; <gdb-patches@sourceware.org>;
<echristo@apple.com>
Sent: Tuesday, October 11, 2005 1:37 AM
Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
> Daniel Jacobowitz wrote:
>
> >Andrew has corrected me off-list: new, non-FSF contributions are not
> >acceptable. I entirely support that position. Is this going to be a
> >problem for MIPS?
> >
> >
>
> OK, we agree to assign copyright of these new files to the FSF. We'll
> resubmit the patch with updated headers.
>
> Nigel
>
[-- Attachment #2: sim.diff --]
[-- Type: application/octet-stream, Size: 8614 bytes --]
Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.10
diff -c -3 -p -r1.10 Makefile.in
*** mips/Makefile.in 16 May 2003 07:11:42 -0000 1.10
--- mips/Makefile.in 11 Oct 2005 21:40:21 -0000
*************** SIM_OBJS = \
*** 47,52 ****
--- 47,53 ----
cp1.o \
interp.o \
mdmx.o \
+ dsp.o \
sim-main.o \
sim-hload.o \
sim-engine.o \
*************** cp1.o: $(srcdir)/cp1.c config.h sim-main
*** 78,83 ****
--- 79,86 ----
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
+ dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
+
multi-run.o: multi-include.h tmp-mach-multi
../igen/igen:
*************** IGEN_INCLUDE=\
*** 94,99 ****
--- 97,103 ----
$(srcdir)/sb1.igen \
$(srcdir)/tx.igen \
$(srcdir)/vr.igen \
+ $(srcdir)/dsp.igen \
# NB: Since these can be built by a number of generators, care
# must be taken to ensure that they are only dependant on
Index: mips/configure.ac
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.ac,v
retrieving revision 1.5
diff -c -3 -p -r1.5 configure.ac
*** mips/configure.ac 16 Jun 2005 15:15:49 -0000 1.5
--- mips/configure.ac 11 Oct 2005 21:40:21 -0000
*************** case "${target}" in
*** 146,164 ****
sim_m16_filter="16"
;;
mipsisa32r2*-*-*) sim_gen=M16
! sim_igen_machine="-M mips32r2,mips16,mips16e"
sim_m16_machine="-M mips16,mips16e,mips32r2"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r2"
;;
mipsisa32*-*-*) sim_gen=M16
! sim_igen_machine="-M mips32,mips16,mips16e"
sim_m16_machine="-M mips16,mips16e,mips32"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32"
;;
mipsisa64r2*-*-*) sim_gen=M16
! sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
--- 146,164 ----
sim_m16_filter="16"
;;
mipsisa32r2*-*-*) sim_gen=M16
! sim_igen_machine="-M mips32r2,mips16,mips16e,dsp"
sim_m16_machine="-M mips16,mips16e,mips32r2"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r2"
;;
mipsisa32*-*-*) sim_gen=M16
! sim_igen_machine="-M mips32,mips16,mips16e,dsp"
sim_m16_machine="-M mips16,mips16e,mips32"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32"
;;
mipsisa64r2*-*-*) sim_gen=M16
! sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,dsp"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
*************** case "${target}" in
*** 169,175 ****
sim_mach_default="mips_sb1"
;;
mipsisa64*-*-*) sim_gen=M16
! sim_igen_machine="-M mips64,mips3d,mips16,mips16e"
sim_m16_machine="-M mips16,mips16e,mips64"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64"
--- 169,175 ----
sim_mach_default="mips_sb1"
;;
mipsisa64*-*-*) sim_gen=M16
! sim_igen_machine="-M mips64,mips3d,mips16,mips16e,dsp"
sim_m16_machine="-M mips16,mips16e,mips64"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64"
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.59
diff -c -3 -p -r1.59 mips.igen
*** mips/mips.igen 16 Jun 2005 15:15:49 -0000 1.59
--- mips/mips.igen 11 Oct 2005 21:40:21 -0000
***************
*** 71,76 ****
--- 71,77 ----
:model:::mips16e:mips16e: // m16e.igen
:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
+ :model:::dsp:dsp: // dsp.igen
// Vendor Extensions
//
***************
*** 2477,2486 ****
*mipsIII:
*mipsIV:
*mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
*vr4100:
*vr5000:
*r3900:
--- 2478,2483 ----
***************
*** 2505,2514 ****
*mipsIII:
*mipsIV:
*mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
*vr4100:
*vr5000:
*r3900:
--- 2502,2507 ----
***************
*** 2607,2616 ****
*mipsIII:
*mipsIV:
*mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
*vr4100:
*vr5000:
*r3900:
--- 2600,2605 ----
***************
*** 2628,2637 ****
*mipsIII:
*mipsIV:
*mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
*vr4100:
*vr5000:
*r3900:
--- 2617,2622 ----
***************
*** 5697,5700 ****
--- 5682,5686 ----
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
+ :include:::dsp.igen
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.27
diff -c -3 -p -r1.27 sim-main.h
*** mips/sim-main.h 12 May 2004 01:42:33 -0000 1.27
--- mips/sim-main.h 11 Oct 2005 21:40:21 -0000
*************** struct _sim_cpu {
*** 312,318 ****
state. */
#ifndef TM_MIPS_H
! #define LAST_EMBED_REGNUM (89)
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
--- 312,318 ----
state. */
#ifndef TM_MIPS_H
! #define LAST_EMBED_REGNUM (96)
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
*************** struct _sim_cpu {
*** 349,354 ****
--- 349,399 ----
#define DEPC (REGISTERS[87])
#define EPC (REGISTERS[88])
+ #define AC0LOIDX (33) /* Must be the same register as LO */
+ #define AC0HIIDX (34) /* Must be the same register as HI */
+ #define AC1LOIDX (90)
+ #define AC1HIIDX (91)
+ #define AC2LOIDX (92)
+ #define AC2HIIDX (93)
+ #define AC3LOIDX (94)
+ #define AC3HIIDX (95)
+
+ #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
+ #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
+
+ #define DSPCRIDX (96) /* DSP control register */
+ #define DSPCR (REGISTERS[DSPCRIDX])
+
+ #define DSPCR_POS_SHIFT (0)
+ #define DSPCR_POS_MASK (0x3f)
+ #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+
+ #define DSPCR_SCOUNT_SHIFT (7)
+ #define DSPCR_SCOUNT_MASK (0x3f)
+ #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+
+ #define DSPCR_CARRY_SHIFT (13)
+ #define DSPCR_CARRY_MASK (1)
+ #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+ #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
+
+ #define DSPCR_EFI_SHIFT (14)
+ #define DSPCR_EFI_MASK (1)
+ #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+ #define DSPCR_EFI (1 << DSPCR_EFI_MASK)
+
+ #define DSPCR_OUFLAG_SHIFT (16)
+ #define DSPCR_OUFLAG_MASK (0xff)
+ #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+ #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
+ #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
+ #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
+ #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
+
+ #define DSPCR_CCOND_SHIFT (24)
+ #define DSPCR_CCOND_MASK (0xf)
+ #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
+
/* All internal state modified by signal_exception() that may need to be
rolled back for passing moment-of-exception image back to gdb. */
unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
*************** INLINE_SIM_MAIN (unsigned16) ifetch16 PA
*** 933,938 ****
--- 978,986 ----
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
extern FILE *tracefh;
+ extern int DSPLO_REGNUM[4];
+ extern int DSPHI_REGNUM[4];
+
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
extern SIM_CORE_SIGNAL_FN mips_core_signal;
Index: testsuite/sim/mips/basic.exp
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/mips/basic.exp,v
retrieving revision 1.5
diff -c -3 -p -r1.5 basic.exp
*** testsuite/sim/mips/basic.exp 11 Apr 2004 06:28:08 -0000 1.5
--- testsuite/sim/mips/basic.exp 11 Oct 2005 21:40:21 -0000
*************** if {[istarget mips*-elf] && [board_info
*** 71,74 ****
--- 71,76 ----
run_sim_test mdmx-ob.s $submodels
run_sim_test mdmx-ob-sb1.s $submodels
+
+ run_sim_test mips32-dsp.s $models
}
[-- Attachment #3: dsp.igen --]
[-- Type: application/octet-stream, Size: 42382 bytes --]
// -*- C -*-
// Simulator definition for the MIPS DSP ASE.
// Copyright (C) 2005 Free Software Foundation, Inc.
// Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
//
// This file is part of GDB, the GNU debugger.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// op: 0 = ADD, 1 = SUB
// sat: 0 = no saturation, 1 = saturation
:function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat
{
int i;
signed32 h0;
signed16 h1, h2;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned32 result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
if (op == 0) // ADD
h0 = (signed32)h1 + (signed32)h2;
else // SUB
h0 = (signed32)h1 - (signed32)h2;
if (((h0 & 0x10000) >> 1) != (h0 & 0x8000))
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
{
if (h0 & 0x10000)
h0 = 0x8000;
else
h0 = 0x7fff;
}
}
result |= ((unsigned32)((unsigned16)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
// op: 0 = ADD, 1 = SUB
:function:::void:do_w_op:int rd, int rs, int rt, int op
{
signed64 h0;
signed32 h1, h2;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned32 result = 0;
h1 = (signed32)v1;
h2 = (signed32)v2;
if (op == 0) // ADD
h0 = (signed64)h1 + (signed64)h2;
else // SUB
h0 = (signed64)h1 - (signed64)h2;
if (((h0 & 0x100000000) >> 1) != (h0 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG4;
if (h0 & 0x100000000)
h0 = 0x80000000;
else
h0 = 0x7fffffff;
}
GPR[rd] = EXTEND32 (h0);
}
// op: 0 = ADD, 1 = SUB
// sat: 0 = no saturation, 1 = saturation
:function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat
{
int i;
unsigned32 h0;
unsigned8 h1, h2;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned32 result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
{
h1 = (unsigned8)(v1 & 0xff);
h2 = (unsigned8)(v2 & 0xff);
if (op == 0) // ADD
h0 = (unsigned32)h1 + (unsigned32)h2;
else // SUB
h0 = (unsigned32)h1 - (unsigned32)h2;
if (h0 & 0x100)
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
{
if (op == 0) // ADD
h0 = 0xff;
else // SUB
h0 = 0;
}
}
result |= ((unsigned32)((unsigned8)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
// op: 0 = left, 1 = right
:function:::void:do_qb_shift:int rd, int rt, int shift, int op
{
int i, j;
unsigned8 h0;
unsigned32 v1 = GPR[rt];
unsigned32 result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
h0 = (unsigned8)(v1 & 0xff);
if (op == 0) // left
{
for (j = 7; j >= 8 - shift; j--)
{
if (h0 & (1<<j))
{
DSPCR |= DSPCR_OUFLAG6;
break;
}
}
h0 = h0 << shift;
}
else // right
h0 = h0 >> shift;
result |= ((unsigned32)h0 << i);
}
GPR[rd] = EXTEND32 (result);
}
// op: 0 = left, 1 = right
// sat: 0 = no saturation/rounding, 1 = saturation/rounding
:function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat
{
int i, j;
signed16 h0;
unsigned32 v1 = GPR[rt];
unsigned32 result = 0;
int setcond;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
h0 = (signed16)(v1 & 0xffff);
if (op == 0) // left
{
setcond = 0;
if (h0 & (1<<15))
{
for (j = 14; j >= 15 - shift; j--)
{
if (!(h0 & (1 << j)))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 1;
break;
}
}
}
else
{
for (j = 14; j >= 15 - shift; j--)
{
if (h0 & (1 << j))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 2;
break;
}
}
}
h0 = h0 << shift;
if (sat == 1)
{
if (setcond == 2)
h0 = 0x7fff;
else if (setcond == 1)
h0 = 0x8000;
}
}
else // right
{
if (sat == 1 && shift != 0)
h0 += (1 << (shift - 1));
h0 = h0 >> shift;
}
result |= ((unsigned32)((unsigned16)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
:function:::void:do_w_shll:int rd, int rt, int shift
{
int i;
unsigned32 v1 = GPR[rt];
unsigned32 result = 0;
int setcond = 0;
if (v1 & (1 << 31))
{
for (i = 30; i >= 31 - shift; i--)
{
if (!(v1 & (1 << i)))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 1;
break;
}
}
}
else
{
for (i = 30; i >= 31 - shift; i--)
{
if (v1 & (1 << i))
{
DSPCR |= DSPCR_OUFLAG6;
setcond = 2;
break;
}
}
}
if (setcond == 2)
result = 0x7fffffff;
else if (setcond == 1)
result = 0x80000000;
else
result = v1 << shift;
GPR[rd] = EXTEND32 (result);
}
:function:::void:do_w_shra:int rd, int rt, int shift
{
unsigned32 result = GPR[rt];
signed32 h0 = (signed32)result;
if (shift != 0)
h0 += (1 << (shift - 1));
h0 = h0 >> shift;
GPR[rd] = EXTEND32 (h0);
}
011111,5.RS,5.RT,5.RD,01010,010000:SPECIAL3:32::ADDQ.PH
"addq.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_op (SD_, RD, RS, RT, 0, 0);
}
011111,5.RS,5.RT,5.RD,01110,010000:SPECIAL3:32::ADDQ_S.PH
"addq_s.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_op (SD_, RD, RS, RT, 0, 1);
}
011111,5.RS,5.RT,5.RD,10110,010000:SPECIAL3:32::ADDQ_S.W
"addq_s.w r<RD>, r<RS>, r<RT>"
*dsp:
{
do_w_op (SD_, RD, RS, RT, 0);
}
011111,5.RS,5.RT,5.RD,00000,010000:SPECIAL3:32::ADDU.QB
"addu.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_op (SD_, RD, RS, RT, 0, 0);
}
011111,5.RS,5.RT,5.RD,00100,010000:SPECIAL3:32::ADDU_S.QB
"addu_s.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_op (SD_, RD, RS, RT, 0, 1);
}
011111,5.RS,5.RT,5.RD,01011,010000:SPECIAL3:32::SUBQ.PH
"subq.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_op (SD_, RD, RS, RT, 1, 0);
}
011111,5.RS,5.RT,5.RD,01111,010000:SPECIAL3:32::SUBQ_S.PH
"subq_s.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_op (SD_, RD, RS, RT, 1, 1);
}
011111,5.RS,5.RT,5.RD,10111,010000:SPECIAL3:32::SUBQ_S.W
"subq_s.w r<RD>, r<RS>, r<RT>"
*dsp:
{
do_w_op (SD_, RD, RS, RT, 1);
}
011111,5.RS,5.RT,5.RD,00001,010000:SPECIAL3:32::SUBU.QB
"subu.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_op (SD_, RD, RS, RT, 1, 0);
}
011111,5.RS,5.RT,5.RD,00101,010000:SPECIAL3:32::SUBU_S.QB
"subu_s.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_op (SD_, RD, RS, RT, 1, 1);
}
011111,5.RS,5.RT,5.RD,10000,010000:SPECIAL3:32::ADDSC
"addsc r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned64 h0;
h0 = (unsigned64)v1 + (unsigned64)v2;
if (h0 & 0x100000000LL)
DSPCR |= DSPCR_CARRY;
GPR[RD] = EXTEND32 (h0);
}
011111,5.RS,5.RT,5.RD,10001,010000:SPECIAL3:32::ADDWC
"addwc r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned64 h0;
signed32 h1 = (signed32) v1;
signed32 h2 = (signed32) v2;
h0 = (signed64)h1 + (signed64)h2
+ (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);
if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
DSPCR |= DSPCR_OUFLAG4;
GPR[RD] = EXTEND32 (h0);
}
011111,5.RS,5.RT,5.RD,10010,010000:SPECIAL3:32::MODSUB
"modsub r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 result = 0;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 decr = v2 & 0xff;
unsigned32 lastindex = (v2 & 0xffff00) >> 8;
if (v1 == 0)
result = lastindex;
else
result = v1 - decr;
GPR[RD] = EXTEND32 (result);
}
011111,5.RS,00000,5.RD,10100,010000:SPECIAL3:32::RADDU.W.QB
"raddu.w.qb r<RD>, r<RS>"
*dsp:
{
int i;
unsigned8 h0;
unsigned32 v1 = GPR[RS];
unsigned32 result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
h0 = (unsigned8)(v1 & 0xff);
result += (unsigned32)h0;
}
GPR[RD] = EXTEND32 (result);
}
011111,00000,5.RT,5.RD,01001,010010:SPECIAL3:32::ABSQ_S.PH
"absq_s.ph r<RD>, r<RT>"
*dsp:
{
int i;
signed16 h0;
unsigned32 v1 = GPR[RT];
unsigned32 result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
h0 = (signed16)(v1 & 0xffff);
if (h0 == (signed16)0x8000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fff;
}
else if (h0 & 0x8000)
h0 = -h0;
result |= ((unsigned32)((unsigned16)h0) << i);
}
GPR[RD] = EXTEND32 (result);
}
011111,00000,5.RT,5.RD,10001,010010:SPECIAL3:32::ABSQ_S.W
"absq_s.w r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
signed32 h0 = (signed32)v1;
if (h0 == (signed32)0x80000000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fffffff;
}
else if (h0 & 0x80000000)
h0 = -h0;
GPR[RD] = EXTEND32 (h0);
}
011111,5.RS,5.RT,5.RD,01100,010001:SPECIAL3:32::PRECRQ.QB.PH
"precrq.qb.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 tempu = (v1 & 0xff000000) >> 24;
unsigned32 tempv = (v1 & 0xff00) >> 8;
unsigned32 tempw = (v2 & 0xff000000) >> 24;
unsigned32 tempx = (v2 & 0xff00) >> 8;
GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
}
011111,5.RS,5.RT,5.RD,10100,010001:SPECIAL3:32::PRECRQ.PH.W
"precrq.ph.w r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 tempu = (v1 & 0xffff0000) >> 16;
unsigned32 tempv = (v2 & 0xffff0000) >> 16;
GPR[RD] = EXTEND32 ((tempu << 16) | tempv);
}
011111,5.RS,5.RT,5.RD,10101,010001:SPECIAL3:32::PRECRQ_RS.PH.W
"precrq_rs.ph.w r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
signed32 h1 = (signed32)v1;
signed32 h2 = (signed32)v2;
signed64 temp1 = (signed64)h1 + (signed64)0x8000;
signed32 temp2;
signed64 temp3 = (signed64)h2 + (signed64)0x8000;
signed32 temp4;
if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp2 = 0x7fff;
}
else
temp2 = (signed32)((temp1 & 0xffff0000) >> 16);
if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp4 = 0x7fff;
}
else
temp4 = (signed32)((temp3 & 0xffff0000) >> 16);
GPR[RD] = EXTEND32 ((temp2 << 16) | temp4);
}
011111,5.RS,5.RT,5.RD,01111,010001:SPECIAL3:32::PRECRQU_S.QB.PH
"precrqu_s.qb.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 tempu, tempv, tempw, tempx;
if (v1 & 0x80000000)
{
DSPCR |= DSPCR_OUFLAG6;
tempu = 0;
}
else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempu = 0xff;
}
else
tempu = (v1 & 0x7f800000) >> 23;
if (v1 & 0x8000)
{
DSPCR |= DSPCR_OUFLAG6;
tempv = 0;
}
else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempv = 0xff;
}
else
tempv = (v1 & 0x7f80) >> 7;
if (v2 & 0x80000000)
{
DSPCR |= DSPCR_OUFLAG6;
tempw = 0;
}
else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempw = 0xff;
}
else
tempw = (v2 & 0x7f800000) >> 23;
if (v2 & 0x8000)
{
DSPCR |= DSPCR_OUFLAG6;
tempx = 0;
}
else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempx = 0xff;
}
else
tempx = (v2 & 0x7f80) >> 7;
GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
}
011111,00000,5.RT,5.RD,01100,010010:SPECIAL3:32::PRECEQ.W.PHL
"preceq.w.phl r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 (v1 & 0xffff0000);
}
011111,00000,5.RT,5.RD,01101,010010:SPECIAL3:32::PRECEQ.W.PHR
"preceq.w.phr r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xffff) << 16);
}
011111,00000,5.RT,5.RD,00100,010010:SPECIAL3:32::PRECEQU.PH.QBL
"precequ.ph.qbl r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff0000) >> 9);
}
011111,00000,5.RT,5.RD,00101,010010:SPECIAL3:32::PRECEQU.PH.QBR
"precequ.ph.qbr r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7);
}
011111,00000,5.RT,5.RD,00110,010010:SPECIAL3:32::PRECEQU.PH.QBLA
"precequ.ph.qbla r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff00) >> 1);
}
011111,00000,5.RT,5.RD,00111,010010:SPECIAL3:32::PRECEQU.PH.QBRA
"precequ.ph.qbra r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff0000) << 7) | ((v1 & 0xff) << 7);
}
011111,00000,5.RT,5.RD,11100,010010:SPECIAL3:32::PRECEU.PH.QBL
"preceu.ph.qbl r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff0000) >> 16);
}
011111,00000,5.RT,5.RD,11101,010010:SPECIAL3:32::PRECEU.PH.QBR
"preceu.ph.qbr r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff);
}
011111,00000,5.RT,5.RD,11110,010010:SPECIAL3:32::PRECEU.PH.QBLA
"preceu.ph.qbla r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff00) >> 8);
}
011111,00000,5.RT,5.RD,11111,010010:SPECIAL3:32::PRECEU.PH.QBRA
"preceu.ph.qbra r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 & 0xff0000) | (v1 & 0xff));
}
011111,00,3.SHIFT3,5.RT,5.RD,00000,010011:SPECIAL3:32::SHLL.QB
"shll.qb r<RD>, r<RT>, <SHIFT3>"
*dsp:
{
do_qb_shift (SD_, RD, RT, SHIFT3, 0);
}
011111,5.RS,5.RT,5.RD,00010,010011:SPECIAL3:32::SHLLV.QB
"shllv.qb r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x7;
do_qb_shift (SD_, RD, RT, shift, 0);
}
011111,0,4.SHIFT4,5.RT,5.RD,01000,010011:SPECIAL3:32::SHLL.PH
"shll.ph r<RD>, r<RT>, <SHIFT4>"
*dsp:
{
do_ph_shift (SD_, RD, RT, SHIFT4, 0, 0);
}
011111,5.RS,5.RT,5.RD,01010,010011:SPECIAL3:32::SHLLV.PH
"shllv.ph r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0xf;
do_ph_shift (SD_, RD, RT, shift, 0, 0);
}
011111,0,4.SHIFT4,5.RT,5.RD,01100,010011:SPECIAL3:32::SHLL_S.PH
"shll_s.ph r<RD>, r<RT>, <SHIFT4>"
*dsp:
{
do_ph_shift (SD_, RD, RT, SHIFT4, 0, 1);
}
011111,5.RS,5.RT,5.RD,01110,010011:SPECIAL3:32::SHLLV_S.PH
"shllv_s.ph r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0xf;
do_ph_shift (SD_, RD, RT, shift, 0, 1);
}
011111,5.SHIFT5,5.RT,5.RD,10100,010011:SPECIAL3:32::SHLL_S.W
"shll_s.w r<RD>, r<RT>, <SHIFT5>"
*dsp:
{
do_w_shll (SD_, RD, RT, SHIFT5);
}
011111,5.RS,5.RT,5.RD,10110,010011:SPECIAL3:32::SHLLV_S.W
"shllv_s.w r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_w_shll (SD_, RD, RT, shift);
}
011111,00,3.SHIFT3,5.RT,5.RD,00001,010011:SPECIAL3:32::SHRL.QB
"shrl.qb r<RD>, r<RT>, <SHIFT3>"
*dsp:
{
do_qb_shift (SD_, RD, RT, SHIFT3, 1);
}
011111,5.RS,5.RT,5.RD,00011,010011:SPECIAL3:32::SHRLV.QB
"shrlv.qb r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x7;
do_qb_shift (SD_, RD, RT, shift, 1);
}
011111,0,4.SHIFT4,5.RT,5.RD,01001,010011:SPECIAL3:32::SHRA.PH
"shra.ph r<RD>, r<RT>, <SHIFT4>"
*dsp:
{
do_ph_shift (SD_, RD, RT, SHIFT4, 1, 0);
}
011111,5.RS,5.RT,5.RD,01011,010011:SPECIAL3:32::SHRAV.PH
"shrav.ph r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0xf;
do_ph_shift (SD_, RD, RT, shift, 1, 0);
}
011111,0,4.SHIFT4,5.RT,5.RD,01101,010011:SPECIAL3:32::SHRA_R.PH
"shra_r.ph r<RD>, r<RT>, <SHIFT4>"
*dsp:
{
do_ph_shift (SD_, RD, RT, SHIFT4, 1, 1);
}
011111,5.RS,5.RT,5.RD,01111,010011:SPECIAL3:32::SHRAV_R.PH
"shrav_r.ph r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0xf;
do_ph_shift (SD_, RD, RT, shift, 1, 1);
}
011111,5.SHIFT5,5.RT,5.RD,10101,010011:SPECIAL3:32::SHRA_R.W
"shra_r.w r<RD>, r<RT>, <SHIFT5>"
*dsp:
{
do_w_shra (SD_, RD, RT, SHIFT5);
}
011111,5.RS,5.RT,5.RD,10111,010011:SPECIAL3:32::SHRAV_R.W
"shrav_r.w r<RD>, r<RT>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_w_shra (SD_, RD, RT, shift);
}
// loc: 0 = qhl, 1 = qhr
:function:::void:do_qb_muleu:int rd, int rs, int rt, int loc
{
int i;
unsigned32 result = 0;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned16 h1, h2;
unsigned32 prod;
if (loc == 0)
v1 >>= 16;
for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16)
{
h1 = (unsigned16)(v1 & 0xff);
h2 = (unsigned16)(v2 & 0xffff);
prod = (unsigned32)h1 * (unsigned32)h2;
if (prod > 0xffff)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0xffff;
}
result |= ((unsigned32)prod << i);
}
GPR[rd] = EXTEND32 (result);
}
011111,5.RS,5.RT,5.RD,00110,010000:SPECIAL3:32::MULEU_S.PH.QBL
"muleu_s.ph.qbl r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_muleu (SD_, RD, RS, RT, 0);
}
011111,5.RS,5.RT,5.RD,00111,010000:SPECIAL3:32::MULEU_S.PH.QBR
"muleu_s.ph.qbr r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_muleu (SD_, RD, RS, RT, 1);
}
011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH
"mulq_rs.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
int i;
unsigned32 result = 0;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
signed16 h1, h2;
signed32 prod;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
prod = (((signed32)h1 * (signed32)h2) << 1) + (signed32)0x8000;
result |= (((unsigned32)prod >> 16) << i);
}
GPR[RD] = EXTEND32 (result);
}
// loc: 0 = phl, 1 = phr
:function:::void:do_ph_muleq:int rd, int rs, int rt, int loc
{
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
signed16 h1, h2;
signed32 prod;
if (loc == 0)
{
h1 = (signed16)(v1 >> 16);
h2 = (signed16)(v2 >> 16);
}
else
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
}
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
prod = ((signed32)h1 * (signed32)h2) << 1;
GPR[rd] = EXTEND32 (prod);
}
011111,5.RS,5.RT,5.RD,11100,010000:SPECIAL3:32::MULEQ_S.W.PHL
"muleq_s.w.phl r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_muleq (SD_, RD, RS, RT, 0);
}
011111,5.RS,5.RT,5.RD,11101,010000:SPECIAL3:32::MULEQ_S.W.PHR
"muleq_s.w.phr r<RD>, r<RS>, r<RT>"
*dsp:
{
do_ph_muleq (SD_, RD, RS, RT, 1);
}
// op: 0 = DPAU 1 = DPSU
// loc: 0 = qbl, 1 = qbr
:function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc
{
int i;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned8 h1, h2;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
if (loc == 0)
{
v1 >>= 16;
v2 >>= 16;
}
for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8)
{
h1 = (unsigned8)(v1 & 0xff);
h2 = (unsigned8)(v2 & 0xff);
if (op == 0) // DPAU
prod += (unsigned64)h1 * (unsigned64)h2;
else // DPSU
prod -= (unsigned64)h1 * (unsigned64)h2;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
011111,5.RS,5.RT,000,2.AC,00011,110000:SPECIAL3:32::DPAU.H.QBL
"dpau.h.qbl ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_qb_dot_product (SD_, AC, RS, RT, 0, 0);
}
011111,5.RS,5.RT,000,2.AC,00111,110000:SPECIAL3:32::DPAU.H.QBR
"dpau.h.qbr ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_qb_dot_product (SD_, AC, RS, RT, 0, 1);
}
011111,5.RS,5.RT,000,2.AC,01011,110000:SPECIAL3:32::DPSU.H.QBL
"dpsu.h.qbl ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_qb_dot_product (SD_, AC, RS, RT, 1, 0);
}
011111,5.RS,5.RT,000,2.AC,01111,110000:SPECIAL3:32::DPSU.H.QBR
"dpsu.h.qbr ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_qb_dot_product (SD_, AC, RS, RT, 1, 1);
}
// op: 0 = DPAQ 1 = DPSQ
:function:::void:do_ph_dot_product:int ac, int rs, int rt, int op
{
int i;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
signed16 h1, h2;
signed32 result;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (signed32)0x7fffffff;
}
else
result = ((signed32)h1 * (signed32)h2) << 1;
if (op == 0) // DPAQ
prod += (signed64)result;
else // DPSQ
prod -= (signed64)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
011111,5.RS,5.RT,000,2.AC,00100,110000:SPECIAL3:32::DPAQ_S.W.PH
"dpaq_s.w.ph ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_dot_product (SD_, AC, RS, RT, 0);
}
011111,5.RS,5.RT,000,2.AC,00101,110000:SPECIAL3:32::DPSQ_S.W.PH
"dpsq_s.w.ph ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_dot_product (SD_, AC, RS, RT, 1);
}
011111,5.RS,5.RT,000,2.AC,00110,110000:SPECIAL3:32::MULSAQ_S.W.PH
"mulsaq_s.w.ph ac<AC>, r<RS>, r<RT>"
*dsp:
{
int i;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
signed16 h1, h2;
signed32 result;
unsigned32 lo = DSPLO(AC);
unsigned32 hi = DSPHI(AC);
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + AC));
result = (signed32) 0x7fffffff;
}
else
result = ((signed32)h1 * (signed32)h2) << 1;
if (i == 0)
prod -= (signed64) result;
else
prod += (signed64) result;
}
DSPLO(AC) = EXTEND32 (prod);
DSPHI(AC) = EXTEND32 (prod >> 32);
}
// op: 0 = DPAQ 1 = DPSQ
:function:::void:do_w_dot_product:int ac, int rs, int rt, int op
{
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
signed32 h1, h2;
signed64 result;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned32 resultlo;
unsigned32 resulthi;
unsigned32 carry;
unsigned64 temp1;
signed64 temp2;
h1 = (signed32) v1;
h2 = (signed32) v2;
if (h1 == 0x80000000 && h2 == 0x80000000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (signed64) 0x7fffffffffffffffLL;
}
else
result = ((signed64)h1 * (signed64)h2) << 1;
resultlo = (unsigned32)(result);
resulthi = (unsigned32)(result >> 32);
if (op ==0) // DPAQ
{
temp1 = (unsigned64)lo + (unsigned64)resultlo;
carry = (unsigned32)((temp1 >> 32) & 1);
temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) +
(signed64)((signed32)carry);
}
else // DPSQ
{
temp1 = (unsigned64)lo - (unsigned64)resultlo;
carry = (unsigned32)((temp1 >> 32) & 1);
temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) -
(signed64)((signed32)carry);
}
if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
if (temp2 & 0x100000000LL)
{
DSPLO(ac) = EXTEND32 (0x00000000);
DSPHI(ac) = EXTEND32 (0x80000000);
}
else
{
DSPLO(ac) = EXTEND32 (0xffffffff);
DSPHI(ac) = EXTEND32 (0x7fffffff);
}
}
else
{
DSPLO(ac) = EXTEND32 (temp1);
DSPHI(ac) = EXTEND32 (temp2);
}
}
011111,5.RS,5.RT,000,2.AC,01100,110000:SPECIAL3:32::DPAQ_SA.L.W
"dpaq_sa.l.w ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_w_dot_product (SD_, AC, RS, RT, 0);
}
011111,5.RS,5.RT,000,2.AC,01101,110000:SPECIAL3:32::DPSQ_SA.L.W
"dpsq_sa.l.w ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_w_dot_product (SD_, AC, RS, RT, 1);
}
// op: 0 = MAQ_S 1 = MAQ_SA
// loc: 0 = phl, 1 = phr
:function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc
{
int i;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
signed16 h1, h2;
signed32 result;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
if (loc == 0)
{
h1 = (signed16)(v1 >> 16);
h2 = (signed16)(v2 >> 16);
}
else
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
}
if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = (signed32)0x7fffffff;
}
else
result = ((signed32)h1 * (signed32)h2) << 1;
prod += (signed64)result;
if (op == 1) // MAQ_SA
{
if (prod & 0x8000000000000000LL)
{
for (i = 62; i >= 31; i--)
{
if (!(prod & ((signed64)1 << i)))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0xffffffff80000000LL;
break;
}
}
}
else
{
for (i = 62; i >= 31; i--)
{
if (prod & ((signed64)1 << i))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0x7fffffff;
break;
}
}
}
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
011111,5.RS,5.RT,000,2.AC,10100,110000:SPECIAL3:32::MAQ_S.W.PHL
"maq_s.w.phl ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_maq (SD_, AC, RS, RT, 0, 0);
}
011111,5.RS,5.RT,000,2.AC,10110,110000:SPECIAL3:32::MAQ_S.W.PHR
"maq_s.w.phr ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_maq (SD_, AC, RS, RT, 0, 1);
}
011111,5.RS,5.RT,000,2.AC,10000,110000:SPECIAL3:32::MAQ_SA.W.PHL
"maq_sa.w.phl ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_maq (SD_, AC, RS, RT, 1, 0);
}
011111,5.RS,5.RT,000,2.AC,10010,110000:SPECIAL3:32::MAQ_SA.W.PHR
"maq_sa.w.phr ac<AC>, r<RS>, r<RT>"
*dsp:
{
do_ph_maq (SD_, AC, RS, RT, 1, 1);
}
011111,00000,5.RT,5.RD,11011,010010:SPECIAL3:32::BITREV
"bitrev r<RD>, r<RT>"
*dsp:
{
int i;
unsigned32 v1 = GPR[RT];
unsigned32 h1 = 0;
for (i = 0; i < 16; i++)
{
if (v1 & (1 << i))
h1 |= (1 << (15 - i));
}
GPR[RD] = EXTEND32 (h1);
}
011111,5.RS,5.RT,00000,00000,001100:SPECIAL3:32::INSV
"insv r<RT>, r<RS>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;
unsigned32 mask1, mask2, mask3, result;
if (size < 32)
mask1 = (1 << size) - 1;
else
mask1 = 0xffffffff;
mask2 = (1 << pos) - 1;
if (pos + size < 32)
mask3 = ~((1 << (pos + size)) - 1);
else
mask3 = 0;
result = (v2 & mask3) | ((v1 & mask1) << pos) | (v2 & mask2);
GPR[RT] = EXTEND32 (result);
}
011111,00,8.IMM8,5.RD,00010,010010:SPECIAL3:32::REPL.QB
"repl.qb r<RD>, <IMM8>"
*dsp:
{
GPR[RD] = EXTEND32 ((IMM8 << 24) | (IMM8 << 16) | (IMM8 << 8) | IMM8);
}
011111,00000,5.RT,5.RD,00011,010010:SPECIAL3:32::REPLV.QB
"replv.qb r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
v1 = v1 & 0xff;
GPR[RD] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1);
}
011111,10.IMM10,5.RD,01010,010010:SPECIAL3:32::REPL.PH
"repl.ph r<RD>, <IMM10>"
*dsp:
{
signed32 v1 = IMM10;
if (v1 & 0x200)
v1 |= 0xfffffc00;
GPR[RD] = EXTEND32 ((v1 << 16) | (v1 & 0xffff));
}
011111,00000,5.RT,5.RD,01011,010010:SPECIAL3:32::REPLV.PH
"replv.ph r<RD>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RT];
v1 = v1 & 0xffff;
GPR[RD] = EXTEND32 ((v1 << 16) | v1);
}
// op: 0 = EQ, 1 = LT, 2 = LE
:function:::void:do_qb_cmpu:int rs, int rt, int op
{
int i, j;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned8 h1, h2;
unsigned32 mask;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (unsigned8)(v1 & 0xff);
h2 = (unsigned8)(v2 & 0xff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
else if (op == 1) // LT
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
else // LE
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
}
}
011111,5.RS,5.RT,00000,00000,010001:SPECIAL3:32::CMPU.EQ.QB
"cmpu.eq.qb r<RS>, r<RT>"
*dsp:
{
do_qb_cmpu (SD_, RS, RT, 0);
}
011111,5.RS,5.RT,00000,00001,010001:SPECIAL3:32::CMPU.LT.QB
"cmpu.lt.qb r<RS>, r<RT>"
*dsp:
{
do_qb_cmpu (SD_, RS, RT, 1);
}
011111,5.RS,5.RT,00000,00010,010001:SPECIAL3:32::CMPU.LE.QB
"cmpu.le.qb r<RS>, r<RT>"
*dsp:
{
do_qb_cmpu (SD_, RS, RT, 2);
}
// op: 0 = EQ, 1 = LT, 2 = LE
:function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op
{
int i, j;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
unsigned8 h1, h2;
unsigned32 result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (unsigned8)(v1 & 0xff);
h2 = (unsigned8)(v2 & 0xff);
if (op == 0) // EQ
result |= ((h1 == h2) << j);
else if (op == 1) // LT
result |= ((h1 < h2) << j);
else // LE
result |= ((h1 <= h2) << j);
}
GPR[rd] = EXTEND32 (result);
}
011111,5.RS,5.RT,5.RD,00100,010001:SPECIAL3:32::CMPGU.EQ.QB
"cmpgu.eq.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_cmpgu (SD_, RD, RS, RT, 0);
}
011111,5.RS,5.RT,5.RD,00101,010001:SPECIAL3:32::CMPGU.LT.QB
"cmpgu.lt.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_cmpgu (SD_, RD, RS, RT, 1);
}
011111,5.RS,5.RT,5.RD,00110,010001:SPECIAL3:32::CMPGU.LE.QB
"cmpgu.le.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
do_qb_cmpgu (SD_, RD, RS, RT, 2);
}
// op: 0 = EQ, 1 = LT, 2 = LE
:function:::void:do_ph_cmpu:int rs, int rt, int op
{
int i, j;
unsigned32 v1 = GPR[rs];
unsigned32 v2 = GPR[rt];
signed16 h1, h2;
unsigned32 mask;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
else if (op == 1) // LT
DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
else // LE
DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
}
}
011111,5.RS,5.RT,00000,01000,010001:SPECIAL3:32::CMP.EQ.PH
"cmp.eq.ph r<RS>, r<RT>"
*dsp:
{
do_ph_cmpu (SD_, RS, RT, 0);
}
011111,5.RS,5.RT,00000,01001,010001:SPECIAL3:32::CMP.LT.PH
"cmp.lt.ph r<RS>, r<RT>"
*dsp:
{
do_ph_cmpu (SD_, RS, RT, 1);
}
011111,5.RS,5.RT,00000,01010,010001:SPECIAL3:32::CMP.LE.PH
"cmp.le.ph r<RS>, r<RT>"
*dsp:
{
do_ph_cmpu (SD_, RS, RT, 2);
}
011111,5.RS,5.RT,5.RD,00011,010001:SPECIAL3:32::PICK.QB
"pick.qb r<RD>, r<RS>, r<RT>"
*dsp:
{
int i, j;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned8 h1, h2;
unsigned32 result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
h1 = (unsigned8)(v1 & 0xff);
h2 = (unsigned8)(v2 & 0xff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
result |= (unsigned32)(h1 << i);
else
result |= (unsigned32)(h2 << i);
}
GPR[RD] = EXTEND32 (result);
}
011111,5.RS,5.RT,5.RD,01011,010001:SPECIAL3:32::PICK.PH
"pick.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
int i, j;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned16 h1, h2;
unsigned32 result = 0;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
h1 = (unsigned16)(v1 & 0xffff);
h2 = (unsigned16)(v2 & 0xffff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
result |= (unsigned32)(h1 << i);
else
result |= (unsigned32)(h2 << i);
}
GPR[RD] = EXTEND32 (result);
}
011111,5.RS,5.RT,5.RD,01110,010001:SPECIAL3:32::PACKRL.PH
"packrl.ph r<RD>, r<RS>, r<RT>"
*dsp:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
GPR[RD] = EXTEND32 ((v1 << 16) + (v2 >> 16));
}
// op: 0 = EXTR, 1 = EXTR_R, 2 = EXTR_RS
:function:::void:do_w_extr:int rt, int ac, int shift, int op
{
int i;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
signed64 result = (signed64)prod;
int setcond = 0;
if (!(prod & 0x8000000000000000LL))
{
for (i = 62; i >= (shift + 31); i--)
{
if (prod & ((unsigned64)1 << i))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 1;
break;
}
}
if (((prod >> (shift - 1)) & 0xffffffffLL) == 0xffffffffLL)
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 1;
}
}
else
{
for (i = 62; i >= (shift + 31); i--)
{
if (!(prod & ((unsigned64)1 << i)))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 2;
break;
}
}
}
if (op == 0) // EXTR
result = result >> shift;
else if (op == 1) // EXTR_R
{
if (shift != 0)
result = ((result >> (shift - 1)) + 1) >> 1;
else
result = result >> shift;
}
else // EXTR_RS
{
if (setcond == 1)
result = 0x7fffffff;
else if (setcond == 2)
result = 0x80000000;
else
{
if (shift != 0)
result = ((result >> (shift - 1)) + 1) >> 1;
else
result = result >> shift;
}
}
GPR[rt] = EXTEND32 (result);
}
011111,5.SHIFT,5.RT,000,2.AC,00000,111000:SPECIAL3:32::EXTR.W
"extr.w r<RT>, ac<AC>, <SHIFT>"
*dsp:
{
do_w_extr (SD_, RT, AC, SHIFT, 0);
}
011111,5.RS,5.RT,000,2.AC,00001,111000:SPECIAL3:32::EXTRV.W
"extrv.w r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_w_extr (SD_, RT, AC, shift, 0);
}
011111,5.SHIFT,5.RT,000,2.AC,00100,111000:SPECIAL3:32::EXTR_R.W
"extr_r.w r<RT>, ac<AC>, <SHIFT>"
*dsp:
{
do_w_extr (SD_, RT, AC, SHIFT, 1);
}
011111,5.RS,5.RT,000,2.AC,00101,111000:SPECIAL3:32::EXTRV_R.W
"extrv_r.w r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_w_extr (SD_, RT, AC, shift, 1);
}
011111,5.SHIFT,5.RT,000,2.AC,00110,111000:SPECIAL3:32::EXTR_RS.W
"extr_rs.w r<RT>, ac<AC>, <SHIFT>"
*dsp:
{
do_w_extr (SD_, RT, AC, SHIFT, 2);
}
011111,5.RS,5.RT,000,2.AC,00111,111000:SPECIAL3:32::EXTRV_RS.W
"extrv_rs.w r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_w_extr (SD_, RT, AC, shift, 2);
}
:function:::void:do_h_extr:int rt, int ac, int shift
{
int i;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
signed64 result = (signed64)prod;
signed64 value = 0xffffffffffff8000LL;
result >>= shift;
if (result > 0x7fff)
{
result = 0x7fff;
DSPCR |= DSPCR_OUFLAG7;
}
else if (result < value)
{
result = value;
DSPCR |= DSPCR_OUFLAG7;
}
GPR[rt] = EXTEND32 (result);
}
011111,5.SHIFT,5.RT,000,2.AC,01110,111000:SPECIAL3:32::EXTR_S.H
"extr_s.h r<RT>, ac<AC>, <SHIFT>"
*dsp:
{
do_h_extr (SD_, RT, AC, SHIFT);
}
011111,5.RS,5.RT,000,2.AC,01111,111000:SPECIAL3:32::EXTRV_S.H
"extrv_s.h r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 shift = GPR[RS] & 0x1f;
do_h_extr (SD_, RT, AC, shift);
}
// op: 0 = EXTP, 1 = EXTPDP
:function:::void:do_extp:int rt, int ac, int size, int op
{
signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
unsigned64 result = 0;
if (pos - (size + 1) >= -1)
{
prod >>= (pos - size);
result = prod & (((unsigned64)1 << (size + 1)) - 1);
DSPCR &= (~DSPCR_EFI_SMASK);
if (op == 1) // EXTPDP
{
if (pos - (size + 1) >= 0)
{
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= ((pos - (size + 1)) & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
}
else if (pos - (size + 1) == -1)
{
DSPCR |= DSPCR_POS_SMASK;
}
}
}
else
{
DSPCR |= DSPCR_EFI;
Unpredictable ();
}
GPR[rt] = EXTEND32 (result);
}
011111,5.SIZE,5.RT,000,2.AC,00010,111000:SPECIAL3:32::EXTP
"extp r<RT>, ac<AC>, <SIZE>"
*dsp:
{
do_extp (SD_, RT, AC, SIZE, 0);
}
011111,5.RS,5.RT,000,2.AC,00011,111000:SPECIAL3:32::EXTPV
"extpv r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 size = GPR[RS] & 0x1f;
do_extp (SD_, RT, AC, size, 0);
}
011111,5.SIZE,5.RT,000,2.AC,01010,111000:SPECIAL3:32::EXTPDP
"extpdp r<RT>, ac<AC>, <SIZE>"
*dsp:
{
do_extp (SD_, RT, AC, SIZE, 1);
}
011111,5.RS,5.RT,000,2.AC,01011,111000:SPECIAL3:32::EXTPDPV
"extpdpv r<RT>, ac<AC>, r<RS>"
*dsp:
{
unsigned32 size = GPR[RS] & 0x1f;
do_extp (SD_, RT, AC, size, 1);
}
:function:::void:do_shilo:int ac, int shift
{
unsigned32 lo = DSPLO(ac);
unsigned32 hi = DSPHI(ac);
unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
if (shift > 31)
shift = shift - 64;
if (shift >= 0)
prod >>= shift;
else
prod <<= (-shift);
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
}
011111,6.SHIFT6,0000,000,2.AC,11010,111000:SPECIAL3:32::SHILO
"shilo ac<AC>, <SHIFT6>"
*dsp:
{
do_shilo (SD_, AC, SHIFT6);
}
011111,5.RS,00000,000,2.AC,11011,111000:SPECIAL3:32::SHILOV
"shilov ac<AC>, r<RS>"
*dsp:
{
signed32 shift = GPR[RS] & 0x3f;
do_shilo (SD_, AC, shift);
}
011111,5.RS,00000,000,2.AC,11111,111000:SPECIAL3:32::MTHLIP
"mthlip r<RS>, ac<AC>"
*dsp:
{
unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
DSPHI(AC) = DSPLO(AC);
DSPLO(AC) = GPR[RS];
if (pos >= 32)
Unpredictable ();
else
pos += 32;
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
}
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHIdsp
"mfhi r<RD>":AC == 0
"mfhi r<RD>, ac<AC>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*dsp:
{
if (AC == 0)
do_mfhi (SD_, RD);
else
GPR[RD] = DSPHI(AC);
}
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLOdsp
"mflo r<RD>":AC == 0
"mflo r<RD>, ac<AC>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*dsp:
{
if (AC == 0)
do_mflo (SD_, RD);
else
GPR[RD] = DSPLO(AC);
}
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHIdsp
"mthi r<RS>":AC == 0
"mthi r<RS>, ac<AC>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*dsp:
{
if (AC == 0)
check_mt_hilo (SD_, HIHISTORY);
DSPHI(AC) = GPR[RS];
}
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLOdsp
"mtlo r<RS>":AC == 0
"mtlo r<RS>, ac<AC>"
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*dsp:
{
if (AC == 0)
check_mt_hilo (SD_, LOHISTORY);
DSPLO(AC) = GPR[RS];
}
011111,5.RS,10.MASK10,10011,111000:SPECIAL3:32::WRDSP
"wrdsp r<RS>":MASK10 == 1111111111
"wrdsp r<RS>, <MASK10>"
*dsp:
{
unsigned32 v1 = GPR[RS];
if (MASK10 & 0x1)
{
DSPCR &= (~DSPCR_POS_SMASK);
DSPCR |= (v1 & DSPCR_POS_SMASK);
}
if (MASK10 & 0x2)
{
DSPCR &= (~DSPCR_SCOUNT_SMASK);
DSPCR |= (v1 & DSPCR_SCOUNT_SMASK);
}
if (MASK10 & 0x4)
{
DSPCR &= (~DSPCR_CARRY_SMASK);
DSPCR |= (v1 & DSPCR_CARRY_SMASK);
}
if (MASK10 & 0x8)
{
DSPCR &= (~DSPCR_OUFLAG_SMASK);
DSPCR |= (v1 & DSPCR_OUFLAG_SMASK);
}
if (MASK10 & 0x10)
{
DSPCR &= (~DSPCR_CCOND_SMASK);
DSPCR |= (v1 & DSPCR_CCOND_SMASK);
}
if (MASK10 & 0x20)
{
DSPCR &= (~DSPCR_EFI_SMASK);
DSPCR |= (v1 & DSPCR_EFI_SMASK);
}
}
011111,10.MASK10,5.RD,10010,111000:SPECIAL3:32::RDDSP
"rddsp r<RD>":MASK10 == 1111111111
"rddsp r<RD>, <MASK10>"
*dsp:
{
unsigned32 result = 0;
if (MASK10 & 0x1)
{
result &= (~DSPCR_POS_SMASK);
result |= (DSPCR & DSPCR_POS_SMASK);
}
if (MASK10 & 0x2)
{
result &= (~DSPCR_SCOUNT_SMASK);
result |= (DSPCR & DSPCR_SCOUNT_SMASK);
}
if (MASK10 & 0x4)
{
result &= (~DSPCR_CARRY_SMASK);
result |= (DSPCR & DSPCR_CARRY_SMASK);
}
if (MASK10 & 0x8)
{
result &= (~DSPCR_OUFLAG_SMASK);
result |= (DSPCR & DSPCR_OUFLAG_SMASK);
}
if (MASK10 & 0x10)
{
result &= (~DSPCR_CCOND_SMASK);
result |= (DSPCR & DSPCR_CCOND_SMASK);
}
if (MASK10 & 0x20)
{
result &= (~DSPCR_EFI_SMASK);
result |= (DSPCR & DSPCR_EFI_SMASK);
}
GPR[RD] = EXTEND32 (result);
}
011111,5.BASE,5.INDEX,5.RD,00110,001010:SPECIAL3:32::LBUX
"lbux r<RD>, r<INDEX>(r<BASE>)"
*dsp:
{
GPR[RD] = do_load (SD_, AccessLength_BYTE, GPR[BASE], GPR[INDEX]);
}
011111,5.BASE,5.INDEX,5.RD,00100,001010:SPECIAL3:32::LHX
"lhx r<RD>, r<INDEX>(r<BASE>)"
*dsp:
{
GPR[RD] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], GPR[INDEX]));
}
011111,5.BASE,5.INDEX,5.RD,00000,001010:SPECIAL3:32::LWX
"lwx r<RD>, r<INDEX>(r<BASE>)"
*dsp:
{
GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
000001,00000,11100,16.OFFSET:REGIMM:32::BPOSGE32
"bposge32 <OFFSET>"
*dsp:
{
unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
address_word offset = EXTEND16 (OFFSET) << 2;
if (pos >= 32)
{
DELAY_SLOT (NIA + offset);
}
}
[-- Attachment #4: dsp.c --]
[-- Type: application/octet-stream, Size: 1086 bytes --]
/* Simulation code for the MIPS DSP ASE.
Copyright (C) 2005 Free Software Foundation, Inc.
Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
int DSPLO_REGNUM[4] =
{
AC0LOIDX,
AC1LOIDX,
AC2LOIDX,
AC3LOIDX,
};
int DSPHI_REGNUM[4] =
{
AC0HIIDX,
AC1HIIDX,
AC2HIIDX,
AC3HIIDX,
};
[-- Attachment #5: mips32-dsp.s --]
[-- Type: application/octet-stream, Size: 36201 bytes --]
# MIPS32 DSP ASE test
# mach: mips32 mips64
#as: -mdsp
#ld: -N -Ttext=0x80010000
#output: *\\npass\\n
# Copyright (C) 2005 Free Software Foundation, Inc.
# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
.include "testutils.inc"
.include "utils-dsp.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test addq.ph"
dspck_dstio addq.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addq.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0
dspck_dstio addq.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0
dspck_dstio addq.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0
dspck_dstio addq.ph, 0x0, 0xffffffff, 0x10001, 0x0, 0x0
writemsg "[2] Test addq_s.ph"
dspck_dstio addq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addq_s.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0
dspck_dstio addq_s.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0
dspck_dstio addq_s.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0
dspck_dstio addq_s.ph, 0xffff0000, 0x1, 0xffffffff, 0x0, 0x0
writemsg "[3] Test addq_s.w"
dspck_dsti addq_s.w, 0x0, 0x0, 0x0, 0x0
dspck_dstio addq_s.w, 0x2, 0x1, 0x1, 0x0, 0x0
dspck_dstio addq_s.w, 0xfffffffe, 0xffffffff, 0xffffffff, 0x0, 0x0
dspck_dstio addq_s.w, 0x0, 0xffffffff, 0x1, 0x0, 0x0
dspck_dstio addq_s.w, 0xffff, 0xffffffff, 0x10000, 0x0, 0x0
writemsg "[4] Test addu.qb"
dspck_dstio addu.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addu.qb, 0x2040000, 0x102ff01, 0x10201ff, 0x0, 0x100000
dspck_dstio addu.qb, 0xfe0001fe, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000
dspck_dstio addu.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0
dspck_dstio addu.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0
writemsg "[5] Test addu_s.qb"
dspck_dstio addu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addu_s.qb, 0x204ffff, 0x102ff01, 0x10201ff, 0x0, 0x100000
dspck_dstio addu_s.qb, 0xfeffffff, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000
dspck_dstio addu_s.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0
dspck_dstio addu_s.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0
writemsg "[6] Test subq.ph"
dspck_dstio subq.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio subq.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0
dspck_dstio subq.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0
dspck_dstio subq.ph, 0x7fff0000, 0xfffe8000, 0x7fff8000, 0x0, 0x100000
dspck_dstio subq.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0
writemsg "[7] Test subq_s.ph"
dspck_dstio subq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio subq_s.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0
dspck_dstio subq_s.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0
dspck_dstio subq_s.ph, 0x0, 0x7fff8000, 0x7fff8000, 0x0, 0x0
dspck_dstio subq_s.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0
writemsg "[8] Test subq_s.w"
dspck_dsti subq_s.w, 0x0, 0x0, 0x0, 0x0
dspck_dsti subq_s.w, 0x0, 0x7fffffff, 0x7fffffff, 0x0
dspck_dstio subq_s.w, 0x7fffffff, 0x0, 0x80000000, 0x0, 0x100000
dspck_dstio subq_s.w, 0x1, 0x2, 0x1, 0x0, 0x0
dspck_dstio subq_s.w, 0xffffffff, 0xfffffffe, 0xffffffff, 0x0, 0x0
writemsg "[9] Test subu.qb"
dspck_dstio subu.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio subu.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0
dspck_dstio subu.qb, 0xfcfdfeff, 0x4030201, 0x8060402, 0x0, 0x100000
dspck_dstio subu.qb, 0x102ff01, 0x2040000, 0x10201ff, 0x0, 0x100000
dspck_dstio subu.qb, 0x7f80ffff, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000
writemsg "[10] Test subu_s.qb"
dspck_dstio subu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio subu_s.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0
dspck_dstio subu_s.qb, 0x0, 0x4030201, 0x8060402, 0x0, 0x100000
dspck_dstio subu_s.qb, 0x1020000, 0x2040000, 0x10201ff, 0x0, 0x100000
dspck_dstio subu_s.qb, 0x7f000000, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000
writemsg "[11] Test addsc"
dspck_dstio addsc, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addsc, 0x1000000, 0x84000000, 0x7d000000, 0x0, 0x2000
dspck_dstio addsc, 0xf1000000, 0x74000000, 0x7d000000, 0x0, 0x0
dspck_dstio addsc, 0x2, 0x1, 0x1, 0x0, 0x0
dspck_dstio addsc, 0xffffffff, 0xfffffffe, 0x1, 0x0, 0x0
writemsg "[12] Test addwc"
dspck_dstio addwc, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio addwc, 0x2, 0x1, 0x1, 0x0, 0x0
dspck_dstio addwc, 0x3, 0x1, 0x1, 0x2000, 0x2000
dspck_dsti addwc, 0x1, 0xffffffff, 0x1, 0x2000
dspck_dsti addwc, 0x11, 0xa, 0x6, 0x2000
writemsg "[13] Test modsub"
dspck_dstio modsub, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio modsub, 0x76, 0x78, 0x7802, 0x0, 0x0
dspck_dstio modsub, 0x74, 0x76, 0x7802, 0x0, 0x0
dspck_dstio modsub, 0x78, 0x0, 0x7802, 0x0, 0x0
dspck_dstio modsub, 0xf9, 0xfc, 0xfe03, 0x0, 0x0
writemsg "[14] Test raddu.w.qb"
dspck_dsio raddu.w.qb, 0x0, 0x0, 0x0, 0x0
dspck_dsio raddu.w.qb, 0x2, 0x1000100, 0x0, 0x0
dspck_dsio raddu.w.qb, 0x4, 0x1010101, 0x0, 0x0
dspck_dsio raddu.w.qb, 0x200, 0xff01ff01, 0x0, 0x0
dspck_dsio raddu.w.qb, 0x3fc, 0xffffffff, 0x0, 0x0
writemsg "[15] Test absq_s.ph"
dspck_dsio absq_s.ph, 0x0, 0x0, 0x0, 0x0
dspck_dsio absq_s.ph, 0x10001, 0xffffffff, 0x0, 0x0
dspck_dsio absq_s.ph, 0x7fff7fff, 0x80008000, 0x0, 0x100000
dspck_dsio absq_s.ph, 0x60000002, 0xa000fffe, 0x0, 0x0
dspck_dsio absq_s.ph, 0x70000004, 0x9000fffc, 0x0, 0x0
writemsg "[16] Test absq_s.w"
dspck_dsio absq_s.w, 0x0, 0x0, 0x0, 0x0
dspck_dsio absq_s.w, 0x1, 0xffffffff, 0x0, 0x0
dspck_dsio absq_s.w, 0x7fffffff, 0x80000000, 0x0, 0x100000
dspck_dsio absq_s.w, 0x40000001, 0xbfffffff, 0x0, 0x0
dspck_dsio absq_s.w, 0x8000001, 0xf7ffffff, 0x0, 0x0
writemsg "[17] Test precrq.qb.ph"
dspck_dstio precrq.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio precrq.qb.ph, 0xff7f4020, 0xffff7fff, 0x40002000, 0x0, 0x0
dspck_dstio precrq.qb.ph, 0xfeba7632, 0xfedcba98, 0x76543210, 0x0, 0x0
dspck_dstio precrq.qb.ph, 0x7632feba, 0x76543210, 0xfedcba98, 0x0, 0x0
dspck_dstio precrq.qb.ph, 0x14589cd, 0x1234567, 0x89abcdef, 0x0, 0x0
writemsg "[18] Test precrq.ph.w"
dspck_dstio precrq.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio precrq.ph.w, 0xffff4000, 0xffff7fff, 0x40002000, 0x0, 0x0
dspck_dstio precrq.ph.w, 0xfedc7654, 0xfedcba98, 0x76543210, 0x0, 0x0
dspck_dstio precrq.ph.w, 0x7654fedc, 0x76543210, 0xfedcba98, 0x0, 0x0
dspck_dstio precrq.ph.w, 0x12389ab, 0x1234567, 0x89abcdef, 0x0, 0x0
writemsg "[19] Test precrq_rs.ph.w"
dspck_dstio precrq_rs.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio precrq_rs.ph.w, 0x7fff0000, 0x7fffffff, 0xffffffff, 0x0, 0x400000
dspck_dstio precrq_rs.ph.w, 0x80008001, 0x80007fff, 0x8000ffff, 0x0, 0x0
dspck_dstio precrq_rs.ph.w, 0xfedd7654, 0xfedcba98, 0x76543210, 0x0, 0x0
dspck_dstio precrq_rs.ph.w, 0x7654fedd, 0x76543210, 0xfedcba98, 0x0, 0x0
writemsg "[20] Test precrqu_s.qb.ph"
dspck_dstio precrqu_s.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio precrqu_s.qb.ph, 0xff8040, 0xffff7fff, 0x40002000, 0x0, 0x400000
dspck_dstio precrqu_s.qb.ph, 0xec64, 0xfedcba98, 0x76543210, 0x0, 0x400000
dspck_dstio precrqu_s.qb.ph, 0xec640000, 0x76543210, 0xfedcba98, 0x0, 0x400000
dspck_dstio precrqu_s.qb.ph, 0x28a0000, 0x1234567, 0x89abcdef, 0x0, 0x400000
writemsg "[21] Test preceq.w.phl"
dspck_dsio preceq.w.phl, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceq.w.phl, 0xffff0000, 0xffffffff, 0x0, 0x0
dspck_dsio preceq.w.phl, 0x80000000, 0x80004000, 0x0, 0x0
dspck_dsio preceq.w.phl, 0xc0010000, 0xc0012001, 0x0, 0x0
dspck_dsio preceq.w.phl, 0x76540000, 0x76543210, 0x0, 0x0
writemsg "[22] Test preceq.w.phr"
dspck_dsio preceq.w.phr, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceq.w.phr, 0xffff0000, 0xffffffff, 0x0, 0x0
dspck_dsio preceq.w.phr, 0x40000000, 0x80004000, 0x0, 0x0
dspck_dsio preceq.w.phr, 0x20010000, 0xc0012001, 0x0, 0x0
dspck_dsio preceq.w.phr, 0x32100000, 0x76543210, 0x0, 0x0
writemsg "[23] Test precequ.ph.qbl"
dspck_dsio precequ.ph.qbl, 0x0, 0x0, 0x0, 0x0
dspck_dsio precequ.ph.qbl, 0x7f807f80, 0xffffffff, 0x0, 0x0
dspck_dsio precequ.ph.qbl, 0x40000000, 0x80004000, 0x0, 0x0
dspck_dsio precequ.ph.qbl, 0x60000080, 0xc0012001, 0x0, 0x0
dspck_dsio precequ.ph.qbl, 0x3b002a00, 0x76543210, 0x0, 0x0
writemsg "[24] Test precequ.ph.qbr"
dspck_dsio precequ.ph.qbr, 0x0, 0x0, 0x0, 0x0
dspck_dsio precequ.ph.qbr, 0x7f807f80, 0xffffffff, 0x0, 0x0
dspck_dsio precequ.ph.qbr, 0x20000000, 0x80004000, 0x0, 0x0
dspck_dsio precequ.ph.qbr, 0x10000080, 0xc0012001, 0x0, 0x0
dspck_dsio precequ.ph.qbr, 0x19000800, 0x76543210, 0x0, 0x0
writemsg "[25] Test precequ.ph.qbla"
dspck_dsio precequ.ph.qbla, 0x0, 0x0, 0x0, 0x0
dspck_dsio precequ.ph.qbla, 0x7f807f80, 0xffffffff, 0x0, 0x0
dspck_dsio precequ.ph.qbla, 0x40002000, 0x80004000, 0x0, 0x0
dspck_dsio precequ.ph.qbla, 0x60001000, 0xc0012001, 0x0, 0x0
dspck_dsio precequ.ph.qbla, 0x3b001900, 0x76543210, 0x0, 0x0
writemsg "[26] Test precequ.ph.qbra"
dspck_dsio precequ.ph.qbra, 0x0, 0x0, 0x0, 0x0
dspck_dsio precequ.ph.qbra, 0x7f807f80, 0xffffffff, 0x0, 0x0
dspck_dsio precequ.ph.qbra, 0x0, 0x80004000, 0x0, 0x0
dspck_dsio precequ.ph.qbra, 0x800080, 0xc0012001, 0x0, 0x0
dspck_dsio precequ.ph.qbra, 0x2a000800, 0x76543210, 0x0, 0x0
writemsg "[27] Test preceu.ph.qbl"
dspck_dsio preceu.ph.qbl, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceu.ph.qbl, 0xff00ff, 0xffffffff, 0x0, 0x0
dspck_dsio preceu.ph.qbl, 0x800000, 0x80004000, 0x0, 0x0
dspck_dsio preceu.ph.qbl, 0xc00001, 0xc0012001, 0x0, 0x0
dspck_dsio preceu.ph.qbl, 0x760054, 0x76543210, 0x0, 0x0
writemsg "[28] Test preceu.ph.qbr"
dspck_dsio preceu.ph.qbr, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceu.ph.qbr, 0xff00ff, 0xffffffff, 0x0, 0x0
dspck_dsio preceu.ph.qbr, 0x400000, 0x80004000, 0x0, 0x0
dspck_dsio preceu.ph.qbr, 0x200001, 0xc0012001, 0x0, 0x0
dspck_dsio preceu.ph.qbr, 0x320010, 0x76543210, 0x0, 0x0
writemsg "[29] Test preceu.ph.qbla"
dspck_dsio preceu.ph.qbla, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceu.ph.qbla, 0xff00ff, 0xffffffff, 0x0, 0x0
dspck_dsio preceu.ph.qbla, 0x800040, 0x80004000, 0x0, 0x0
dspck_dsio preceu.ph.qbla, 0xc00020, 0xc0012001, 0x0, 0x0
dspck_dsio preceu.ph.qbla, 0x760032, 0x76543210, 0x0, 0x0
writemsg "[30] Test preceu.ph.qbra"
dspck_dsio preceu.ph.qbra, 0x0, 0x0, 0x0, 0x0
dspck_dsio preceu.ph.qbra, 0xff00ff, 0xffffffff, 0x0, 0x0
dspck_dsio preceu.ph.qbra, 0x0, 0x80004000, 0x0, 0x0
dspck_dsio preceu.ph.qbra, 0x10001, 0xc0012001, 0x0, 0x0
dspck_dsio preceu.ph.qbra, 0x540010, 0x76543210, 0x0, 0x0
writemsg "[31] Test shll.qb"
dspck_dtsaio shll.qb, 0x0, 0x0, 0, 0x0, 0x0
dspck_dtsai shll.qb, 0x202fefe, 0x101ffff, 1, 0x0
dspck_dtsai shll.qb, 0xfefe0002, 0x7fff8081, 1, 0x0
dspck_dtsai shll.qb, 0xfcfc0020, 0x7fff8008, 2, 0x0
dspck_dtsai shll.qb, 0x68b0d868, 0x6db6db6d, 3, 0x0
writemsg "[32] Test shllv.qb"
dspck_dstio shllv.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dsti shllv.qb, 0x202fefe, 0x101ffff, 0x1, 0x0
dspck_dsti shllv.qb, 0xfefe0002, 0x7fff8081, 0x1, 0x0
dspck_dsti shllv.qb, 0xfcfc0020, 0x7fff8008, 0x2, 0x0
dspck_dsti shllv.qb, 0x68b0d868, 0x6db6db6d, 0x3, 0x0
writemsg "[33] Test shll.ph"
dspck_dtsaio shll.ph, 0x0, 0x0, 0, 0x0, 0x0
dspck_dtsaio shll.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0
dspck_dtsaio shll.ph, 0xfffe0000, 0x7fff8000, 1, 0x0, 0x400000
dspck_dtsaio shll.ph, 0xfffc0020, 0x7fff8008, 2, 0x0, 0x400000
dspck_dtsaio shll.ph, 0x6db0db68, 0x6db6db6d, 3, 0x0, 0x400000
writemsg "[34] Test shllv.ph"
dspck_dstio shllv.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio shllv.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0
dspck_dstio shllv.ph, 0xfffe0000, 0x7fff8000, 0x1, 0x0, 0x400000
dspck_dstio shllv.ph, 0xfffc0020, 0x7fff8008, 0x2, 0x0, 0x400000
dspck_dstio shllv.ph, 0x6db0db68, 0x6db6db6d, 0x3, 0x0, 0x400000
writemsg "[35] Test shll_s.ph"
dspck_dtsaio shll_s.ph, 0x0, 0x0, 0, 0x0, 0x0
dspck_dtsaio shll_s.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0
dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8000, 1, 0x0, 0x400000
dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8008, 2, 0x0, 0x400000
dspck_dtsaio shll_s.ph, 0x7fff8000, 0x6db6db6d, 3, 0x0, 0x400000
writemsg "[36] Test shllv_s.ph"
dspck_dstio shllv_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio shllv_s.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0
dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8000, 0x1, 0x0, 0x400000
dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8008, 0x2, 0x0, 0x400000
dspck_dstio shllv_s.ph, 0x7fff8000, 0x6db6db6d, 0x3, 0x0, 0x400000
writemsg "[37] Test shll_s.w"
dspck_dtsaio shll_s.w, 0x0, 0x0, 0, 0x0, 0x0
dspck_dtsaio shll_s.w, 0x3fffe, 0x1ffff, 1, 0x0, 0x0
dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8000, 1, 0x0, 0x400000
dspck_dtsaio shll_s.w, 0x80000000, 0x80000000, 1, 0x0, 0x400000
dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8008, 2, 0x0, 0x400000
writemsg "[38] Test shllv_s.w"
dspck_dstio shllv_s.w, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio shllv_s.w, 0x3fffe, 0x1ffff, 0x1, 0x0, 0x0
dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8000, 0x1, 0x0, 0x400000
dspck_dstio shllv_s.w, 0x80000000, 0x80000000, 0x1, 0x0, 0x400000
dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8008, 0x2, 0x0, 0x400000
writemsg "[39] Test shrl.qb"
dspck_dtsaio shrl.qb, 0x0, 0x0, 0, 0x0, 0x0
dspck_dtsai shrl.qb, 0x7f7f, 0x101ffff, 1, 0x0
dspck_dtsai shrl.qb, 0x3f7f4040, 0x7fff8081, 1, 0x0
dspck_dtsai shrl.qb, 0x1f3f2002, 0x7fff8008, 2, 0x0
dspck_dtsai shrl.qb, 0xd161b0d, 0x6db6db6d, 3, 0x0
writemsg "[40] Test shrlv.qb"
dspck_dstio shrlv.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dsti shrlv.qb, 0x7f7f, 0x101ffff, 0x1, 0x0
dspck_dsti shrlv.qb, 0x3f7f4040, 0x7fff8081, 0x1, 0x0
dspck_dsti shrlv.qb, 0x1f3f2002, 0x7fff8008, 0x2, 0x0
dspck_dsti shrlv.qb, 0xd161b0d, 0x6db6db6d, 0x3, 0x0
writemsg "[41] Test shra.ph"
dspck_dtsaio shra.ph, 0x10001, 0x20002, 1, 0x0, 0x0
dspck_dtsaio shra.ph, 0x10006, 0x10106f6f, 12, 0x0, 0x0
dspck_dtsaio shra.ph, 0x1c000, 0x28000, 1, 0x0, 0x0
dspck_dtsaio shra.ph, 0x2f800, 0x208000, 4, 0x0, 0x0
dspck_dtsaio shra.ph, 0xfc01fc00, 0x80208000, 5, 0x0, 0x0
writemsg "[42] Test shrav.ph"
dspck_dstio shrav.ph, 0x10001, 0x20002, 0x1, 0x0, 0x0
dspck_dstio shrav.ph, 0x10006, 0x10106f6f, 0xc, 0x0, 0x0
dspck_dstio shrav.ph, 0x1c000, 0x28000, 0x1, 0x0, 0x0
dspck_dstio shrav.ph, 0x2f800, 0x208000, 0x4, 0x0, 0x0
dspck_dstio shrav.ph, 0xfc01fc00, 0x80208000, 0x5, 0x0, 0x0
writemsg "[43] Test shra_r.ph"
dspck_dtsaio shra_r.ph, 0x20001, 0x30002, 1, 0x0, 0x0
dspck_dtsaio shra_r.ph, 0x10001, 0x20001, 1, 0x0, 0x0
dspck_dtsaio shra_r.ph, 0x10001, 0x10001, 1, 0x0, 0x0
dspck_dtsaio shra_r.ph, 0x0, 0x10001, 2, 0x0, 0x0
writemsg "[44] Test shrav_r.ph"
dspck_dstio shrav_r.ph, 0x20001, 0x30002, 0x1, 0x0, 0x0
dspck_dstio shrav_r.ph, 0x10001, 0x20001, 0x1, 0x0, 0x0
dspck_dstio shrav_r.ph, 0x10001, 0x10001, 0x1, 0x0, 0x0
dspck_dstio shrav_r.ph, 0x0, 0x10001, 0x2, 0x0, 0x0
writemsg "[45] Test shra_r.w"
dspck_dtsaio shra_r.w, 0x1, 0x2, 1, 0x0, 0x0
dspck_dtsaio shra_r.w, 0xffff8000, 0x80000000, 16, 0x0, 0x0
dspck_dtsaio shra_r.w, 0x8001, 0x10001, 1, 0x0, 0x0
dspck_dtsaio shra_r.w, 0x1, 0x10001, 17, 0x0, 0x0
dspck_dtsaio shra_r.w, 0xffffc001, 0x80010001, 17, 0x0, 0x0
writemsg "[46] Test shrav_r.w"
dspck_dstio shrav_r.w, 0x1, 0x2, 0x1, 0x0, 0x0
dspck_dstio shrav_r.w, 0xffff8000, 0x80000000, 0x10, 0x0, 0x0
dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x1, 0x0, 0x0
dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x21, 0x0, 0x0
dspck_dstio shrav_r.w, 0x4000, 0x10001, 0x2, 0x0, 0x0
writemsg "[47] Test muleu_s.ph.qbl"
dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_dstio muleu_s.ph.qbl, 0x0, 0xffffffff, 0x0, 0x0, 0x0
dspck_dstio muleu_s.ph.qbl, 0x10001, 0x1010101, 0x10001, 0x0, 0x0
dspck_dstio muleu_s.ph.qbl, 0x10000, 0x1000001, 0x10001, 0x0, 0x0
writemsg "[48] Test muleu_s.ph.qbr"
dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_dstio muleu_s.ph.qbr, 0x0, 0xffffffff, 0x0, 0x0, 0x0
dspck_dstio muleu_s.ph.qbr, 0x10001, 0x1010101, 0x10001, 0x0, 0x0
dspck_dstio muleu_s.ph.qbr, 0x1, 0x1000001, 0x10001, 0x0, 0x0
writemsg "[49] Test mulq_rs.ph"
dspck_dstio mulq_rs.ph, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio mulq_rs.ph, 0x0, 0x1, 0x1, 0x0, 0x0
dspck_dstio mulq_rs.ph, 0x20000000, 0x40007fff, 0x40000000, 0x0, 0x0
dspck_dstio mulq_rs.ph, 0x33330000, 0x66660000, 0x40007fff, 0x0, 0x0
dspck_dstio mulq_rs.ph, 0xccd3332, 0x66666666, 0x10003fff, 0x0, 0x0
writemsg "[50] Test muleq_s.w.phl"
dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_dstio muleq_s.w.phl, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0xc000c000, 0x0, 0x0
dspck_dstio muleq_s.w.phl, 0x0, 0x80008000, 0x0, 0x0, 0x0
writemsg "[51] Test muleq_s.w.phr"
dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_dstio muleq_s.w.phr, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0xc000c000, 0x0, 0x0
dspck_dstio muleq_s.w.phr, 0x0, 0x80008000, 0x0, 0x0, 0x0
writemsg "[52] Test dpau.h.qbl"
dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpau.h.qbl, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0
dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0
writemsg "[53] Test dpau.h.qbr"
dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpau.h.qbr, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0
dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0
writemsg "[54] Test dpsu.h.qbl"
dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpsu.h.qbl, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpsu.h.qbl, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0
dspck_astio dpsu.h.qbl, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0
writemsg "[55] Test dpsu.h.qbr"
dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpsu.h.qbr, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpsu.h.qbr, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x1000001, 0x0, 0x0
dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0
dspck_astio dpsu.h.qbr, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0
writemsg "[56] Test dpaq_s.w.ph"
dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffc0004, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0
dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffffffe, 0x80008000, 0x80008000, 0x0, 0xf0000
dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0xa0000000, 0x40002000, 0x80008000, 0x0, 0x0
dspck_astio dpaq_s.w.ph, 0xffffffff, 0xa0000000, 0xffffffff, 0x88000000, 0x10000800, 0x80008000, 0x0, 0x0
writemsg "[57] Test dpsq_s.w.ph"
dspck_astio dpsq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpsq_s.w.ph, 0x0, 0xfffc0004, 0x0, 0x0, 0x7fff7fff, 0x7fff7fff, 0x0, 0x0
dspck_astio dpsq_s.w.ph, 0x0, 0xfffffffe, 0x0, 0x0, 0x80008000, 0x80008000, 0x0, 0xf0000
dspck_astio dpsq_s.w.ph, 0xffffffff, 0xa0000000, 0x0, 0x0, 0x40002000, 0x80008000, 0x0, 0x0
dspck_astio dpsq_s.w.ph, 0xffffffff, 0x88000000, 0xffffffff, 0xa0000000, 0x10000800, 0x80008000, 0x0, 0x0
writemsg "[58] Test mulsaq_s.w.ph"
dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x4000, 0xc0000000, 0x0, 0x0
dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0x60010000, 0x80004000, 0x7fff4000, 0x0, 0x0
dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x5fffffff, 0x80004000, 0x80004000, 0x0, 0xf0000
dspck_astio mulsaq_s.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0xfffc0003, 0x7fff8001, 0x7fff7fff, 0x0, 0x0
writemsg "[59] Test dpaq_sa.l.w"
dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7ffffffe, 0x2, 0x7fffffff, 0x7fffffff, 0x0, 0x0
dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7fffffff, 0xffffffff, 0x80000000, 0x80000000, 0x0, 0xf0000
dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0xc0000000, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0
dspck_astio dpaq_sa.l.w, 0x20000000, 0x0, 0x0, 0x40000000, 0xe0000000, 0x7fffffff, 0x0, 0x0
writemsg "[60] Test dpsq_sa.l.w"
dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio dpsq_sa.l.w, 0x7fffffff, 0xffffffff, 0x0, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000
dspck_astio dpsq_sa.l.w, 0x80000000, 0x0, 0x80000000, 0x0, 0x80000000, 0x80000000, 0x0, 0xf0000
dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x80000000, 0x1, 0x80000000, 0x80000000, 0x0, 0xf0000
dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x3fffffff, 0x80000000, 0xc0000000, 0x7fffffff, 0x0, 0x0
writemsg "[61] Test maq_s.w.phl"
dspck_astio maq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_astio maq_s.w.phl, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0
writemsg "[62] Test maq_s.w.phr"
dspck_astio maq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000, 0x0, 0x0
dspck_astio maq_s.w.phr, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_s.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0
writemsg "[63] Test maq_sa.w.phl"
dspck_astio maq_sa.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0
dspck_astio maq_sa.w.phl, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0
writemsg "[64] Test maq_sa.w.phr"
dspck_astio maq_sa.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x0, 0x40004000, 0x0, 0x0
dspck_astio maq_sa.w.phr, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, 0x7fff7fff, 0x0, 0x0, 0x0
dspck_astio maq_sa.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000, 0x0, 0x0
writemsg "[65] Test bitrev"
dspck_dsio bitrev, 0x0, 0x0, 0x0, 0x0
dspck_dsio bitrev, 0x1, 0x8000, 0x0, 0x0
dspck_dsio bitrev, 0x8000, 0x1, 0x0, 0x0
dspck_dsio bitrev, 0xc0c0, 0x1010303, 0x0, 0x0
dspck_dsio bitrev, 0x1, 0xffff8000, 0x0, 0x0
writemsg "[66] Test insv"
dspck_tsi insv, 0xf0caf0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x311
dspck_tsi insv, 0x7fffffe, 0x0, 0x7ffffff, 0xd01
dspck_tsi insv, 0x3fff, 0x0, 0x3fff, 0x700
dspck_tsi insv, 0xf0f2f0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x28f
dspck_tsi insv, 0x3fc, 0x0, 0x3ff, 0x402
writemsg "[67] Test repl.qb"
dspck_dIio repl.qb, 0x0, 0, 0x0, 0x0
dspck_dIio repl.qb, 0x1010101, 1, 0x0, 0x0
dspck_dIio repl.qb, 0xffffffff, 255, 0x0, 0x0
dspck_dIio repl.qb, 0x7f7f7f7f, 127, 0x0, 0x0
dspck_dIio repl.qb, 0xfefefefe, 254, 0x0, 0x0
writemsg "[68] Test replv.qb"
dspck_dsio replv.qb, 0x0, 0x0, 0x0, 0x0
dspck_dsio replv.qb, 0x1010101, 0x1, 0x0, 0x0
dspck_dsio replv.qb, 0xffffffff, 0xff, 0x0, 0x0
dspck_dsio replv.qb, 0x7f7f7f7f, 0x37f, 0x0, 0x0
dspck_dsio replv.qb, 0xfefefefe, 0xfffffffe, 0x0, 0x0
writemsg "[69] Test repl.ph"
dspck_dIio repl.ph, 0x0, 0, 0x0, 0x0
dspck_dIio repl.ph, 0x10001, 1, 0x0, 0x0
dspck_dIio repl.ph, 0xffffffff, -1, 0x0, 0x0
dspck_dIio repl.ph, 0xff7fff7f, -129, 0x0, 0x0
dspck_dIio repl.ph, 0xfffefffe, -2, 0x0, 0x0
writemsg "[70] Test replv.ph"
dspck_dsio replv.ph, 0x0, 0x0, 0x0, 0x0
dspck_dsio replv.ph, 0x10001, 0x1, 0x0, 0x0
dspck_dsio replv.ph, 0xffffffff, 0x5555ffff, 0x0, 0x0
dspck_dsio replv.ph, 0x37f037f, 0x37f, 0x0, 0x0
dspck_dsio replv.ph, 0xfffefffe, 0xfffffffe, 0x0, 0x0
writemsg "[71] Test cmpu.eq.qb"
dspck_stio cmpu.eq.qb, 0x0, 0x0, 0x0, 0xf000000
dspck_stio cmpu.eq.qb, 0xffffffff, 0x0, 0x0, 0x0
dspck_stio cmpu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0
dspck_stio cmpu.eq.qb, 0x10203, 0x4050607, 0x0, 0x0
dspck_stio cmpu.eq.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0
writemsg "[72] Test cmpu.lt.qb"
dspck_stio cmpu.lt.qb, 0x0, 0x0, 0x0, 0x0
dspck_stio cmpu.lt.qb, 0xffffffff, 0x0, 0x0, 0x0
dspck_stio cmpu.lt.qb, 0x0, 0xffffffff, 0x0, 0xf000000
dspck_stio cmpu.lt.qb, 0x10203, 0x4050607, 0x0, 0xf000000
dspck_stio cmpu.lt.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000
writemsg "[73] Test cmpu.le.qb"
dspck_stio cmpu.le.qb, 0x0, 0x0, 0x0, 0xf000000
dspck_stio cmpu.le.qb, 0xffffffff, 0x0, 0x0, 0x0
dspck_stio cmpu.le.qb, 0x0, 0xffffffff, 0x0, 0xf000000
dspck_stio cmpu.le.qb, 0x10203, 0x4050607, 0x0, 0xf000000
dspck_stio cmpu.le.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000
writemsg "[74] Test cmpgu.eq.qb"
dspck_dstio cmpgu.eq.qb, 0xf, 0x0, 0x0, 0x0, 0x0
dspck_dstio cmpgu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0
dspck_dstio cmpgu.eq.qb, 0x0, 0x0, 0xffffffff, 0x0, 0x0
dspck_dstio cmpgu.eq.qb, 0x0, 0x10203, 0x4050607, 0x0, 0x0
dspck_dstio cmpgu.eq.qb, 0x0, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0
writemsg "[75] Test cmpgu.lt.qb"
dspck_dstio cmpgu.lt.qb, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_dstio cmpgu.lt.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0
dspck_dstio cmpgu.lt.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0
dspck_dstio cmpgu.lt.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0
dspck_dstio cmpgu.lt.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0
writemsg "[76] Test cmpgu.le.qb"
dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0x0, 0x0, 0x0
dspck_dstio cmpgu.le.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0
dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0
dspck_dstio cmpgu.le.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0
dspck_dstio cmpgu.le.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0
writemsg "[77] Test cmp.eq.ph"
dspck_stio cmp.eq.ph, 0x0, 0x0, 0x0, 0x3000000
dspck_stio cmp.eq.ph, 0x0, 0xffffffff, 0x0, 0x0
dspck_stio cmp.eq.ph, 0xffffffff, 0x0, 0x0, 0x0
dspck_stio cmp.eq.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0
dspck_stio cmp.eq.ph, 0x11112222, 0x33334444, 0x0, 0x0
writemsg "[78] Test cmp.lt.ph"
dspck_stio cmp.lt.ph, 0x0, 0x0, 0x0, 0x0
dspck_stio cmp.lt.ph, 0x0, 0xffffffff, 0x0, 0x0
dspck_stio cmp.lt.ph, 0xffffffff, 0x0, 0x0, 0x3000000
dspck_stio cmp.lt.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0
dspck_stio cmp.lt.ph, 0x11112222, 0x33334444, 0x0, 0x3000000
writemsg "[79] Test cmp.le.ph"
dspck_stio cmp.le.ph, 0x0, 0x0, 0x0, 0x3000000
dspck_stio cmp.le.ph, 0x0, 0xffffffff, 0x0, 0x0
dspck_stio cmp.le.ph, 0xffffffff, 0x0, 0x0, 0x3000000
dspck_stio cmp.le.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0
dspck_stio cmp.le.ph, 0x11112222, 0x33334444, 0x0, 0x3000000
writemsg "[80] Test pick.qb"
dspck_dsti pick.qb, 0x0, 0x0, 0x0, 0x0
dspck_dsti pick.qb, 0x0, 0xffffffff, 0x0, 0x0
dspck_dsti pick.qb, 0xffffffff, 0xffffffff, 0x0, 0xf000000
dspck_dsti pick.qb, 0xff, 0xffffffff, 0x0, 0x1000000
dspck_dsti pick.qb, 0xff00, 0xffffffff, 0x0, 0x2000000
writemsg "[81] Test pick.ph"
dspck_dsti pick.ph, 0x0, 0x0, 0x0, 0x0
dspck_dsti pick.ph, 0x0, 0xffffffff, 0x0, 0x0
dspck_dsti pick.ph, 0xffffffff, 0xffffffff, 0x0, 0x3000000
dspck_dsti pick.ph, 0xffff, 0xffffffff, 0x0, 0x1000000
dspck_dsti pick.ph, 0xffff0000, 0xffffffff, 0x0, 0x2000000
writemsg "[82] Test packrl.ph"
dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0
dspck_dstio packrl.ph, 0x0000ffff, 0x00000000, 0xffff0000, 0x0, 0x0
dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x0000ffff, 0x0, 0x0
dspck_dstio packrl.ph, 0x00005555, 0x00000000, 0x5555aaaa, 0x0, 0x0
dspck_dstio packrl.ph, 0x0000aaaa, 0x00000000, 0xaaaa5555, 0x0, 0x0
writemsg "[83] Test extr.w"
dspck_atsaio extr.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsaio extr.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000
dspck_atsaio extr.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsaio extr.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsaio extr.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[84] Test extr_r.w"
dspck_atsaio extr_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsaio extr_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000
dspck_atsaio extr_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsaio extr_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsaio extr_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[85] Test extr_rs.w"
dspck_atsaio extr_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsaio extr_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000
dspck_atsaio extr_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsaio extr_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsaio extr_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[86] Test extr_s.h"
dspck_atsaio extr_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsaio extr_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000
dspck_atsaio extr_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000
dspck_atsaio extr_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsaio extr_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000
writemsg "[87] Test extrv_s.h"
dspck_atsio extrv_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsio extrv_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000
dspck_atsio extrv_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000
dspck_atsio extrv_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsio extrv_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000
writemsg "[88] Test extrv.w"
dspck_atsio extrv.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsio extrv.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x800000
dspck_atsio extrv.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsio extrv.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsio extrv.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[89] Test extrv_r.w"
dspck_atsio extrv_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsio extrv_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000
dspck_atsio extrv_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsio extrv_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsio extrv_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[90] Test extrv_rs.w"
dspck_atsio extrv_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0
dspck_atsio extrv_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x800000
dspck_atsio extrv_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0
dspck_atsio extrv_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0
dspck_atsio extrv_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0
writemsg "[91] Test extp"
dspck_tasiimom extp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f
dspck_tasiimom extp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000
dspck_tasiim extp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f
dspck_tasiim extp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f
writemsg "[92] Test extpv"
dspck_tasimom extpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f
dspck_tasimom extpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000
dspck_tasim extpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f
dspck_tasim extpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f
writemsg "[93] Test extpdp"
dspck_tasiimom extpdp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f
dspck_tasiimom extpdp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000
dspck_tasiim extpdp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f
dspck_tasiim extpdp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f
writemsg "[94] Test extpdpv"
dspck_tasimom extpdpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f
dspck_tasimom extpdpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x4000
dspck_tasim extpdpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f
dspck_tasim extpdpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f
writemsg "[95] Test shilo"
dspck_asaio shilo, 0x0, 0x0, 0x0, 0x0, 0, 0x0, 0x0
dspck_asaio shilo, 0x1, 0x80000000, 0x1, 0x80000000, 0, 0x0, 0x0
dspck_asaio shilo, 0x1, 0x80000000, 0x3, 0x0, -1, 0x0, 0x0
dspck_asaio shilo, 0x1, 0x80000000, 0x6, 0x0, -2, 0x0, 0x0
dspck_asaio shilo, 0x1, 0x80000000, 0x18, 0x0, -4, 0x0, 0x0
writemsg "[96] Test shilov"
dspck_asio shilov, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
dspck_asio shilov, 0x1, 0x80000000, 0x1, 0x80000000, 0x0, 0x0, 0x0
dspck_asio shilov, 0x1, 0x80000000, 0x3, 0x0, 0xffffffff, 0x0, 0x0
dspck_asio shilov, 0x1, 0x80000000, 0x6, 0x0, 0xfffffffe, 0x0, 0x0
dspck_asio shilov, 0x1, 0x80000000, 0x18, 0x0, 0xfffffffc, 0x0, 0x0
writemsg "[97] Test mthlip"
dspck_saio mthlip, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20
dspck_saio mthlip, 0x0, 0x1, 0x1, 0x2, 0x2, 0x8, 0x28
dspck_saio mthlip, 0xffffffff, 0xffff1234, 0xffff1234, 0xfffffffe, 0xfffffffe, 0x10, 0x30
dspck_saio mthlip, 0xdeadbeef, 0x1234, 0x1234, 0xbeefdead, 0xbeefdead, 0x18, 0x38
writemsg "[98] Test wrdsp"
dspck_wrdsp 0x0, 0x0, 0x0, 0x0
dspck_wrdsp 0x4000, 0x20, 0x0, 0x4000
dspck_wrdsp 0xffffffff, 0x3f, 0x0, 0x0fff7fbf
dspck_wrdsp 0x3f, 0x1, 0x0, 0x3f
dspck_wrdsp 0x1f80, 0x2, 0x0, 0x1f80
writemsg "[99] Test rddsp"
dspck_rddsp 0x0, 0x0, 0x0
dspck_rddsp 0x0, 0x0, 0xffffffff
dspck_rddsp 0x3f, 0x1, 0xffffffff
dspck_rddsp 0x1f80, 0x2, 0x0fff7fbf
dspck_rddsp 0x2000, 0x4, 0x0fff7fbf
writemsg "[100] Test lbux"
.data
mydata:
.byte 0x12
.byte 0x34
.byte 0x56
.byte 0x78
.byte 0x9a
.byte 0xbc
.byte 0xde
.byte 0xf0
.previous
dspck_load lbux, 0x12, 0x0, mydata
dspck_load lbux, 0x34, 0x1, mydata
dspck_load lbux, 0x56, 0x2, mydata
dspck_load lbux, 0x78, 0x3, mydata
dspck_load lbux, 0x9a, 0x4, mydata
dspck_load lbux, 0xbc, 0x5, mydata
dspck_load lbux, 0xde, 0x6, mydata
dspck_load lbux, 0xf0, 0x7, mydata
writemsg "[101] Test lhx"
.data
myhdata:
.hword 0x1234
.hword 0x5678
.hword 0x9abc
.hword 0xdef0
.previous
dspck_load lhx, 0x1234, 0x0, myhdata
dspck_load lhx, 0x5678, 0x2, myhdata
dspck_load lhx, 0xffff9abc, 0x4, myhdata
dspck_load lhx, 0xffffdef0, 0x6, myhdata
writemsg "[102] Test lwx"
.data
mywdata:
.word 0x12345678
.word 0x9abcdef0
.word 0x13579abc
.word 0xffff0001
.previous
dspck_load lwx, 0x12345678, 0x0, mywdata
dspck_load lwx, 0x9abcdef0, 0x4, mywdata
dspck_load lwx, 0x13579abc, 0x8, mywdata
dspck_load lwx, 0xffff0001, 0xc, mywdata
writemsg "[103] Test bposge32"
dspck_bposge32 0x0, 0
dspck_bposge32 0x1f, 0
dspck_bposge32 0x20, 1
dspck_bposge32 0x3f, 1
pass
.end DIAG
[-- Attachment #6: utils-dsp.inc --]
[-- Type: application/octet-stream, Size: 8735 bytes --]
# MIPS DSP ASE simulator testsuite utility functions.
# Copyright (C) 2005 Free Software Foundation, Inc.
# Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
# $4, $5, $6, $7, $ac0, $ac1, $ac2, $ac3 are used as temps by the macros
# defined here.
# If a != b, jump to _fail.
# Otherwise, fall through.
.macro dsp_assert a, b
beq \a, \b, 1f
nop
j _fail
nop
1:
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, s, t)
# Check if crout == dsp control register
.macro dspck_dstio inst, d, s, t, crin, crout
li $4, \crin
wrdsp $4
li $4, \s
li $5, \t
\inst $6, $4, $5
li $7, \d
dsp_assert $6, $7
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# (inst s, t)
# Check if crout == dsp control register
.macro dspck_stio inst, s, t, crin, crout
li $4, \crin
wrdsp $4
li $4, \s
li $5, \t
\inst $4, $5
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, s, t)
.macro dspck_dsti inst, d, s, t, crin
li $4, \crin
wrdsp $4
li $4, \s
li $5, \t
\inst $6, $4, $5
li $7, \d
dsp_assert $6, $7
.endm
# Set dsp control register <= crin
# Check if tou == (inst tin, s)
.macro dspck_tsi inst, tou, tin, s, crin
li $4, \crin
wrdsp $4
li $4, \s
li $5, \tin
\inst $5, $4
li $6, \tou
dsp_assert $5, $6
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, imm)
# Check if crout == dsp control register
.macro dspck_dIio inst, d, imm, crin, crout
li $4, \crin
wrdsp $4
\inst $5, \imm
li $6, \d
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, s)
# Check if crout == dsp control register
.macro dspck_dsio inst, d, s, crin, crout
li $4, \crin
wrdsp $4
li $4, \s
\inst $6, $4
li $7, \d
dsp_assert $6, $7
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, t, sa)
# Check if crout == dsp control register
.macro dspck_dtsaio inst, d, t, sa, crin, crout
li $4, \crin
wrdsp $4
li $4, \t
\inst $6, $4, \sa
li $7, \d
dsp_assert $6, $7
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Check if d == (inst ?, t, sa)
.macro dspck_dtsai inst, d, t, sa, crin
li $4, \crin
wrdsp $4
li $4, \t
\inst $6, $4, \sa
li $7, \d
dsp_assert $6, $7
.endm
# Set dsp control register <= crin
# Set $ac3 <= {hiin, loin}
# (inst $ac3, s, t)
# Check if {hiou, loou} == $ac3
# Check if (crout & 0x80000) == (dsp control register & 0x80000)
.macro dspck_astio inst, hiin, loin, hiou, loou, s, t, crin, crout
li $4, \crin
wrdsp $4
li $4, \hiin
mthi $4, $ac3
li $4, \loin
mtlo $4, $ac3
li $4, \s
li $5, \t
\inst $ac3, $4, $5
li $4, \hiou
mfhi $5, $ac3
dsp_assert $4, $5
li $4, \loou
mflo $5, $ac3
dsp_assert $4, $5
li $4, \crout
and $4, $4, 0x80000
rddsp $5
and $5, $5, 0x80000
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Set $ac1 <= {hi, lo}
# Check if t == (inst ? $ac1, sa)
# Check if crout == dsp control register
.macro dspck_atsaio inst, hi, lo, t, sa, crin, crout
li $4, \crin
wrdsp $4
li $4, \hi
mthi $4, $ac1
li $4, \lo
mtlo $4, $ac1
\inst $5, $ac1, \sa
li $6, \t
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Set $ac1 <= {hi, lo}
# Check if t == (inst ? $ac1, s)
# Check if crout == dsp control register
.macro dspck_atsio inst, hi, lo, t, s, crin, crout
li $4, \crin
wrdsp $4
li $4, \hi
mthi $4, $ac1
li $4, \lo
mtlo $4, $ac1
li $4, \s
\inst $5, $ac1, $4
li $6, \t
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= (crin & crinmask)
# Set $ac2 <= {hi, lo}
# Check if t == (inst ? $ac2, size)
# Check if (crout & croutmask) == (dsp control register & croutmask)
.macro dspck_tasiimom inst, hi, lo, t, size, crin, crinmask, crout, croutmask
li $4, \crin
and $4, \crinmask
wrdsp $4
li $4, \hi
mthi $4, $ac2
li $4, \lo
mtlo $4, $ac2
\inst $5, $ac2, \size
li $6, \t
dsp_assert $5, $6
li $4, \crout
and $4, \croutmask
rddsp $5
and $5, \croutmask
dsp_assert $4, $5
.endm
# Set dsp control register <= (crin & crinmask)
# Set $ac2 <= {hi, lo}
# Check if t == (inst ? $ac2, size)
.macro dspck_tasiim inst, hi, lo, t, size, crin, crinmask
li $4, \crin
and $4, \crinmask
wrdsp $4
li $4, \hi
mthi $4, $ac2
li $4, \lo
mtlo $4, $ac2
\inst $5, $ac2, \size
li $6, \t
dsp_assert $5, $6
.endm
# Set dsp control register <= (crin & crinmask)
# Set $ac2 <= {hi, lo}
# Check if t == (inst ? $ac2, s)
# Check if (crout & croutmask) == (dsp control register & croutmask)
.macro dspck_tasimom inst, hi, lo, t, s, crin, crinmask, crout, croutmask
li $4, \crin
and $4, \crinmask
wrdsp $4
li $4, \hi
mthi $4, $ac2
li $4, \lo
mtlo $4, $ac2
li $4, \s
\inst $5, $ac2, $4
li $6, \t
dsp_assert $5, $6
li $4, \crout
and $4, \croutmask
rddsp $5
and $5, \croutmask
dsp_assert $4, $5
.endm
# Set dsp control register <= (crin & crinmask)
# Set $ac2 <= {hi, lo}
# Check if t == (inst ? $ac2, s)
.macro dspck_tasim inst, hi, lo, t, s, crin, crinmask
li $4, \crin
and $4, \crinmask
wrdsp $4
li $4, \hi
mthi $4, $ac2
li $4, \lo
mtlo $4, $ac2
li $4, \s
\inst $5, $ac2, $4
li $6, \t
dsp_assert $5, $6
.endm
# Set dsp control register <= crin
# Set $ac0 <= {hi, lo}
# (inst $ac0, shift)
# Check if $ac0 == {hio, loo}
# Check if crout == dsp control register
.macro dspck_asaio inst, hi, lo, hio, loo, shift, crin, crout
li $4, \crin
wrdsp $4
li $4, \hi
mthi $4, $ac0
li $4, \lo
mtlo $4, $ac0
\inst $ac0, \shift
mfhi $5, $ac0
li $6, \hio
dsp_assert $5, $6
mflo $5, $ac0
li $6, \loo
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Set $ac0 <= {hi, lo}
# (inst $ac0, s)
# Check if $ac0 == {hio, loo}
# Check if crout == dsp control register
.macro dspck_asio inst, hi, lo, hio, loo, s, crin, crout
li $4, \crin
wrdsp $4
li $4, \hi
mthi $4, $ac0
li $4, \lo
mtlo $4, $ac0
li $4, \s
\inst $ac0, $4
mfhi $5, $ac0
li $6, \hio
dsp_assert $5, $6
mflo $5, $ac0
li $6, \loo
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# Set $ac3 <= {hi, lo}
# Check if s == (inst ? $ac3)
# Check if $ac3 == {hio, loo}
# Check if crout == dsp control register
.macro dspck_saio inst, hi, lo, hio, loo, s, crin, crout
li $4, \crin
wrdsp $4
li $4, \hi
mthi $4, $ac3
li $4, \lo
mtlo $4, $ac3
li $5, \s
\inst $5, $ac3
mfhi $5, $ac3
li $6, \hio
dsp_assert $5, $6
mflo $5, $ac3
li $6, \loo
dsp_assert $5, $6
li $4, \crout
rddsp $5
dsp_assert $4, $5
.endm
# Set dsp control register <= crin
# (wrdsp s, m)
# Check if crout == dsp control register
.macro dspck_wrdsp s, m, crin, crout
li $4, \crin
wrdsp $4
li $5, \s
wrdsp $5, \m
li $6, \crout
rddsp $7
dsp_assert $6, $7
.endm
# Set dsp control register <= crin
# Check if d == (rddsp ?, m)
.macro dspck_rddsp d, m, crin
li $4, \crin
wrdsp $4
rddsp $5, \m
li $6, \d
dsp_assert $5, $6
.endm
# Check if d == (inst i(b))
.macro dspck_load inst, d, i, b
li $4, \i
la $5, \b
\inst $6, $4($5)
li $7, \d
dsp_assert $6, $7
.endm
# Set dsp control register <= crin
# Check if bposge32 is taken or not as expected in r
# (1 => taken, 0 => not taken)
.macro dspck_bposge32 crin, r
li $4, \crin
wrdsp $4
li $5, 1
bposge32 1f
nop
li $5, 0
1:
li $6, \r
dsp_assert $5, $6
.endm
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-10-10 23:47 ` Daniel Jacobowitz
2005-10-11 8:37 ` Nigel Stephens
@ 2005-10-11 22:07 ` Eric Christopher
2005-12-15 12:47 ` Chao-ying Fu
1 sibling, 1 reply; 18+ messages in thread
From: Eric Christopher @ 2005-10-11 22:07 UTC (permalink / raw)
To: Daniel Jacobowitz; +Cc: Nigel Stephens, Chao-ying Fu, gdb-patches
>
> [Meanwhile, Eric, when this is settled I intend to approve the code
> changes; if you feel like reviewing it after the fact, I'm sure MIPS
> will be able to correct any problems.]
I did a once-over not too long ago and they seemed fine to me. I just
hadn't had a chance to go over them at any more detail with the
manual.
-eric
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-10-11 22:07 ` Eric Christopher
@ 2005-12-15 12:47 ` Chao-ying Fu
2005-12-16 22:14 ` Eric Christopher
0 siblings, 1 reply; 18+ messages in thread
From: Chao-ying Fu @ 2005-12-15 12:47 UTC (permalink / raw)
To: Eric Christopher, Daniel Jacobowitz
Cc: Thekkath, Radhika, gdb-patches, Nigel Stephens
Hello,
Did you have a chance to go over the MIPS DSP ASE manual?
Could we check in the patch? Thanks a lot!
Regards,
Chao-ying
----- Original Message -----
From: "Eric Christopher" <echristo@apple.com>
To: "Daniel Jacobowitz" <drow@false.org>
Cc: "Nigel Stephens" <nigel@mips.com>; "Chao-ying Fu" <fu@mips.com>;
<gdb-patches@sourceware.org>
Sent: Tuesday, October 11, 2005 2:05 PM
Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
> >
> > [Meanwhile, Eric, when this is settled I intend to approve the code
> > changes; if you feel like reviewing it after the fact, I'm sure MIPS
> > will be able to correct any problems.]
>
> I did a once-over not too long ago and they seemed fine to me. I just
> hadn't had a chance to go over them at any more detail with the
> manual.
>
> -eric
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-12-15 12:47 ` Chao-ying Fu
@ 2005-12-16 22:14 ` Eric Christopher
2005-12-17 20:04 ` Daniel Jacobowitz
0 siblings, 1 reply; 18+ messages in thread
From: Eric Christopher @ 2005-12-16 22:14 UTC (permalink / raw)
To: Chao-ying Fu
Cc: Daniel Jacobowitz, Thekkath, Radhika, gdb-patches, Nigel Stephens
On Dec 13, 2005, at 3:31 PM, Chao-ying Fu wrote:
> Hello,
>
> Did you have a chance to go over the MIPS DSP ASE manual?
> Could we check in the patch? Thanks a lot!
As far as I'm concerned go ahead. I didn't see anything glaring when I
took a look and I'm sure you can fix it up after the fact.
-eric
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-12-16 22:14 ` Eric Christopher
@ 2005-12-17 20:04 ` Daniel Jacobowitz
2005-12-17 23:06 ` Chao-ying Fu
0 siblings, 1 reply; 18+ messages in thread
From: Daniel Jacobowitz @ 2005-12-17 20:04 UTC (permalink / raw)
To: Eric Christopher
Cc: Chao-ying Fu, Thekkath, Radhika, gdb-patches, Nigel Stephens
On Wed, Dec 14, 2005 at 10:11:23AM -0800, Eric Christopher wrote:
>
> On Dec 13, 2005, at 3:31 PM, Chao-ying Fu wrote:
>
> >Hello,
> >
> > Did you have a chance to go over the MIPS DSP ASE manual?
> >Could we check in the patch? Thanks a lot!
>
> As far as I'm concerned go ahead. I didn't see anything glaring when I
> took a look and I'm sure you can fix it up after the fact.
Yes, please go ahead.
--
Daniel Jacobowitz
CodeSourcery, LLC
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
2005-12-17 20:04 ` Daniel Jacobowitz
@ 2005-12-17 23:06 ` Chao-ying Fu
0 siblings, 0 replies; 18+ messages in thread
From: Chao-ying Fu @ 2005-12-17 23:06 UTC (permalink / raw)
To: Daniel Jacobowitz, Eric Christopher
Cc: Thekkath, Radhika, gdb-patches, Nigel Stephens
Thanks a lot! The patch was checked in.
Regards,
Chao-ying
----- Original Message -----
From: "Daniel Jacobowitz" <drow@false.org>
To: "Eric Christopher" <echristo@apple.com>
Cc: "Chao-ying Fu" <fu@mips.com>; "Thekkath, Radhika" <radhika@mips.com>;
<gdb-patches@sourceware.org>; "Nigel Stephens" <nigel@mips.com>
Sent: Wednesday, December 14, 2005 10:13 AM
Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE
> On Wed, Dec 14, 2005 at 10:11:23AM -0800, Eric Christopher wrote:
> >
> > On Dec 13, 2005, at 3:31 PM, Chao-ying Fu wrote:
> >
> > >Hello,
> > >
> > > Did you have a chance to go over the MIPS DSP ASE manual?
> > >Could we check in the patch? Thanks a lot!
> >
> > As far as I'm concerned go ahead. I didn't see anything glaring when I
> > took a look and I'm sure you can fix it up after the fact.
>
> Yes, please go ahead.
>
> --
> Daniel Jacobowitz
> CodeSourcery, LLC
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2005-12-15 0:01 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2005-09-07 23:10 [patch ping2] Simulator Supports for MIPS32 DSP ASE Chao-ying Fu
2005-09-10 3:56 ` Daniel Jacobowitz
2005-09-12 11:22 ` Nigel Stephens
2005-09-12 12:53 ` Daniel Jacobowitz
[not found] ` <4325846F.5090809@mips.com>
2005-09-12 13:43 ` Daniel Jacobowitz
2005-10-10 23:47 ` Daniel Jacobowitz
2005-10-11 8:37 ` Nigel Stephens
2005-10-11 21:59 ` Chao-ying Fu
2005-10-11 22:07 ` Eric Christopher
2005-12-15 12:47 ` Chao-ying Fu
2005-12-16 22:14 ` Eric Christopher
2005-12-17 20:04 ` Daniel Jacobowitz
2005-12-17 23:06 ` Chao-ying Fu
2005-09-14 23:10 ` Chao-ying Fu
2005-09-14 23:38 ` Eric Christopher
2005-09-17 20:45 ` Daniel Jacobowitz
2005-09-23 22:21 ` Chao-ying Fu
2005-09-23 22:23 ` Eric Christopher
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