From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20208 invoked by alias); 11 Oct 2005 21:59:15 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 19888 invoked by uid 22791); 11 Oct 2005 21:59:11 -0000 Received: from 209-232-97-206.ded.pacbell.net (HELO dns0.mips.com) (209.232.97.206) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Tue, 11 Oct 2005 21:59:11 +0000 Received: from mercury.mips.com (sbcns-dmz [209.232.97.193]) by dns0.mips.com (8.12.11/8.12.11) with ESMTP id j9BLvsH7012509; Tue, 11 Oct 2005 14:57:55 -0700 (PDT) Received: from exchange.MIPS.COM (exchange [192.168.20.29]) by mercury.mips.com (8.12.9/8.12.11) with ESMTP id j9BLvt17014120; Tue, 11 Oct 2005 14:57:55 -0700 (PDT) Received: from pcfu ([192.168.20.169]) by exchange.MIPS.COM with Microsoft SMTPSVC(6.0.3790.211); Tue, 11 Oct 2005 14:57:56 -0700 Message-ID: <000d01c5ceae$d1f03960$a914a8c0@MIPS.COM> Reply-To: "Chao-ying Fu" From: "Chao-ying Fu" To: "Nigel Stephens" , "Daniel Jacobowitz" Cc: "Thekkath, Radhika" , , References: <001501c5b401$143d8430$a914a8c0@MIPS.COM> <20050910035633.GA24152@nevyn.them.org> <432564A1.4040004@mips.com> <20050912125331.GA26666@nevyn.them.org> <4325846F.5090809@mips.com> <20051010234710.GA10033@nevyn.them.org> <434B79B0.9010006@mips.com> Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE Date: Tue, 11 Oct 2005 21:59:00 -0000 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_000A_01C5CE74.255828F0" X-SW-Source: 2005-10/txt/msg00102.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-length: 2783 Hi, Here is the revised patch for MIPS32 DSP ASE. We changed the copyright to FSF for our new files. Tested with two configurations. No new regressions. Is it ok to commit? Thanks! Regards, Chao-ying 1. --target=mipsisa32-elf Test Run By fu on Tue Oct 11 14:02:10 2005 Target is mipsisa32-unknown-elf Host is i686-pc-linux-gnu === sim Summary === # of expected passes 22 2. --target=mipsisa64-elf Test Run By fu on Tue Oct 11 14:23:31 2005 Target is mipsisa64-unknown-elf Host is i686-pc-linux-gnu === sim Summary === # of expected passes 45 # of unexpected failures 1 sim/mips/ChangeLog 2005-10-11 Chao-ying Fu * Makefile.in (SIM_OBJS): Add dsp.o. (dsp.o): New dependency. (IGEN_INCLUDE): Add dsp.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, mipsisa64*-*-*): Add dsp to sim_igen_machine. * configure: Regenerate. * mips.igen: Add dsp model and include dsp.igen. (MFHI, MFLO, MTHI, MTLO): Remove *mips32, *mips32r2, *mips64, *mips64r2, because these instructions are extended in DSP ASE. * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of adding 6 DSP accumulator registers and 1 DSP control register. (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, DSPCR_CCOND_SMASK): New define. (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. * dsp.c, dsp.igen: New files for MIPS DSP ASE. sim/testsuite/sim/mips/ChangeLog 2005-10-11 Chao-ying Fu * basic.exp: Run the dsp test. * utils-dsp.inc: New file. * mips32-dsp.s: New test. ----- Original Message ----- From: "Nigel Stephens" To: "Daniel Jacobowitz" Cc: "Chao-ying Fu" ; ; Sent: Tuesday, October 11, 2005 1:37 AM Subject: Re: [patch ping2] Simulator Supports for MIPS32 DSP ASE > Daniel Jacobowitz wrote: > > >Andrew has corrected me off-list: new, non-FSF contributions are not > >acceptable. I entirely support that position. Is this going to be a > >problem for MIPS? > > > > > > OK, we agree to assign copyright of these new files to the FSF. We'll > resubmit the patch with updated headers. > > Nigel > ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: application/octet-stream; name="sim.diff" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="sim.diff" Content-length: 10346 Index: mips/Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/mips/Makefile.in,v=0A= retrieving revision 1.10=0A= diff -c -3 -p -r1.10 Makefile.in=0A= *** mips/Makefile.in 16 May 2003 07:11:42 -0000 1.10=0A= --- mips/Makefile.in 11 Oct 2005 21:40:21 -0000=0A= *************** SIM_OBJS =3D \=0A= *** 47,52 ****=0A= --- 47,53 ----=0A= cp1.o \=0A= interp.o \=0A= mdmx.o \=0A= + dsp.o \=0A= sim-main.o \=0A= sim-hload.o \=0A= sim-engine.o \=0A= *************** cp1.o: $(srcdir)/cp1.c config.h sim-main=0A= *** 78,83 ****=0A= --- 79,86 ----=0A= =20=20=0A= mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h=0A= =20=20=0A= + dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h=0A= +=20=0A= multi-run.o: multi-include.h tmp-mach-multi=0A= =20=20=0A= ../igen/igen:=0A= *************** IGEN_INCLUDE=3D\=0A= *** 94,99 ****=0A= --- 97,103 ----=0A= $(srcdir)/sb1.igen \=0A= $(srcdir)/tx.igen \=0A= $(srcdir)/vr.igen \=0A= + $(srcdir)/dsp.igen \=0A= =20=20=0A= # NB: Since these can be built by a number of generators, care=0A= # must be taken to ensure that they are only dependant on=0A= Index: mips/configure.ac=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/mips/configure.ac,v=0A= retrieving revision 1.5=0A= diff -c -3 -p -r1.5 configure.ac=0A= *** mips/configure.ac 16 Jun 2005 15:15:49 -0000 1.5=0A= --- mips/configure.ac 11 Oct 2005 21:40:21 -0000=0A= *************** case "${target}" in=0A= *** 146,164 ****=0A= sim_m16_filter=3D"16"=0A= ;;=0A= mipsisa32r2*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips32r2,mips16,mips16e"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips32r2"=0A= sim_igen_filter=3D"32,f"=0A= sim_mach_default=3D"mipsisa32r2"=0A= ;;=0A= mipsisa32*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips32,mips16,mips16e"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips32"=0A= sim_igen_filter=3D"32,f"=0A= sim_mach_default=3D"mipsisa32"=0A= ;;=0A= mipsisa64r2*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips64r2,mips3d,mips16,mips16e"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips64r2"=0A= sim_igen_filter=3D"32,64,f"=0A= sim_mach_default=3D"mipsisa64r2"=0A= --- 146,164 ----=0A= sim_m16_filter=3D"16"=0A= ;;=0A= mipsisa32r2*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips32r2,mips16,mips16e,dsp"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips32r2"=0A= sim_igen_filter=3D"32,f"=0A= sim_mach_default=3D"mipsisa32r2"=0A= ;;=0A= mipsisa32*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips32,mips16,mips16e,dsp"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips32"=0A= sim_igen_filter=3D"32,f"=0A= sim_mach_default=3D"mipsisa32"=0A= ;;=0A= mipsisa64r2*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips64r2,mips3d,mips16,mips16e,dsp"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips64r2"=0A= sim_igen_filter=3D"32,64,f"=0A= sim_mach_default=3D"mipsisa64r2"=0A= *************** case "${target}" in=0A= *** 169,175 ****=0A= sim_mach_default=3D"mips_sb1"=0A= ;;=0A= mipsisa64*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips64,mips3d,mips16,mips16e"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips64"=0A= sim_igen_filter=3D"32,64,f"=0A= sim_mach_default=3D"mipsisa64"=0A= --- 169,175 ----=0A= sim_mach_default=3D"mips_sb1"=0A= ;;=0A= mipsisa64*-*-*) sim_gen=3DM16=0A= ! sim_igen_machine=3D"-M mips64,mips3d,mips16,mips16e,dsp"=0A= sim_m16_machine=3D"-M mips16,mips16e,mips64"=0A= sim_igen_filter=3D"32,64,f"=0A= sim_mach_default=3D"mipsisa64"=0A= Index: mips/mips.igen=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/mips/mips.igen,v=0A= retrieving revision 1.59=0A= diff -c -3 -p -r1.59 mips.igen=0A= *** mips/mips.igen 16 Jun 2005 15:15:49 -0000 1.59=0A= --- mips/mips.igen 11 Oct 2005 21:40:21 -0000=0A= ***************=0A= *** 71,76 ****=0A= --- 71,77 ----=0A= :model:::mips16e:mips16e: // m16e.igen=0A= :model:::mips3d:mips3d: // mips3d.igen=0A= :model:::mdmx:mdmx: // mdmx.igen=0A= + :model:::dsp:dsp: // dsp.igen=0A= =20=20=0A= // Vendor Extensions=0A= //=0A= ***************=0A= *** 2477,2486 ****=0A= *mipsIII:=0A= *mipsIV:=0A= *mipsV:=0A= - *mips32:=0A= - *mips32r2:=0A= - *mips64:=0A= - *mips64r2:=0A= *vr4100:=0A= *vr5000:=0A= *r3900:=0A= --- 2478,2483 ----=0A= ***************=0A= *** 2505,2514 ****=0A= *mipsIII:=0A= *mipsIV:=0A= *mipsV:=0A= - *mips32:=0A= - *mips32r2:=0A= - *mips64:=0A= - *mips64r2:=0A= *vr4100:=0A= *vr5000:=0A= *r3900:=0A= --- 2502,2507 ----=0A= ***************=0A= *** 2607,2616 ****=0A= *mipsIII:=0A= *mipsIV:=0A= *mipsV:=0A= - *mips32:=0A= - *mips32r2:=0A= - *mips64:=0A= - *mips64r2:=0A= *vr4100:=0A= *vr5000:=0A= *r3900:=0A= --- 2600,2605 ----=0A= ***************=0A= *** 2628,2637 ****=0A= *mipsIII:=0A= *mipsIV:=0A= *mipsV:=0A= - *mips32:=0A= - *mips32r2:=0A= - *mips64:=0A= - *mips64r2:=0A= *vr4100:=0A= *vr5000:=0A= *r3900:=0A= --- 2617,2622 ----=0A= ***************=0A= *** 5697,5700 ****=0A= --- 5682,5686 ----=0A= :include:::sb1.igen=0A= :include:::tx.igen=0A= :include:::vr.igen=0A= + :include:::dsp.igen=0A= =20=20=0A= Index: mips/sim-main.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/mips/sim-main.h,v=0A= retrieving revision 1.27=0A= diff -c -3 -p -r1.27 sim-main.h=0A= *** mips/sim-main.h 12 May 2004 01:42:33 -0000 1.27=0A= --- mips/sim-main.h 11 Oct 2005 21:40:21 -0000=0A= *************** struct _sim_cpu {=0A= *** 312,318 ****=0A= state. */=0A= =20=20=0A= #ifndef TM_MIPS_H=0A= ! #define LAST_EMBED_REGNUM (89)=0A= #define NUM_REGS (LAST_EMBED_REGNUM + 1)=0A= =20=20=0A= #define FP0_REGNUM 38 /* Floating point register 0 (single floa= t) */=0A= --- 312,318 ----=0A= state. */=0A= =20=20=0A= #ifndef TM_MIPS_H=0A= ! #define LAST_EMBED_REGNUM (96)=0A= #define NUM_REGS (LAST_EMBED_REGNUM + 1)=0A= =20=20=0A= #define FP0_REGNUM 38 /* Floating point register 0 (single floa= t) */=0A= *************** struct _sim_cpu {=0A= *** 349,354 ****=0A= --- 349,399 ----=0A= #define DEPC (REGISTERS[87])=0A= #define EPC (REGISTERS[88])=0A= =20=20=0A= + #define AC0LOIDX (33) /* Must be the same register as LO */=0A= + #define AC0HIIDX (34) /* Must be the same register as HI */=0A= + #define AC1LOIDX (90)=0A= + #define AC1HIIDX (91)=0A= + #define AC2LOIDX (92)=0A= + #define AC2HIIDX (93)=0A= + #define AC3LOIDX (94)=0A= + #define AC3HIIDX (95)=0A= +=20=0A= + #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])=0A= + #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])=0A= +=20=0A= + #define DSPCRIDX (96) /* DSP control register */=0A= + #define DSPCR (REGISTERS[DSPCRIDX])=0A= +=20=0A= + #define DSPCR_POS_SHIFT (0)=0A= + #define DSPCR_POS_MASK (0x3f)=0A= + #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)=0A= +=20=0A= + #define DSPCR_SCOUNT_SHIFT (7)=0A= + #define DSPCR_SCOUNT_MASK (0x3f)=0A= + #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)=0A= +=20=0A= + #define DSPCR_CARRY_SHIFT (13)=0A= + #define DSPCR_CARRY_MASK (1)=0A= + #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)=0A= + #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)=0A= +=20=0A= + #define DSPCR_EFI_SHIFT (14)=0A= + #define DSPCR_EFI_MASK (1)=0A= + #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)=0A= + #define DSPCR_EFI (1 << DSPCR_EFI_MASK)=0A= +=20=0A= + #define DSPCR_OUFLAG_SHIFT (16)=0A= + #define DSPCR_OUFLAG_MASK (0xff)=0A= + #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)=0A= + #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))=0A= + #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))=0A= + #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))=0A= + #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))=0A= +=20=0A= + #define DSPCR_CCOND_SHIFT (24)=0A= + #define DSPCR_CCOND_MASK (0xf)=0A= + #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)=0A= +=20=0A= /* All internal state modified by signal_exception() that may need to b= e=0A= rolled back for passing moment-of-exception image back to gdb. */=0A= unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];=0A= *************** INLINE_SIM_MAIN (unsigned16) ifetch16 PA=0A= *** 933,938 ****=0A= --- 978,986 ----=0A= void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type,= SIM_ADDR address, int width, char *comment, ...));=0A= extern FILE *tracefh;=0A= =20=20=0A= + extern int DSPLO_REGNUM[4];=0A= + extern int DSPHI_REGNUM[4];=0A= +=20=0A= INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, a= ddress_word cia));=0A= extern SIM_CORE_SIGNAL_FN mips_core_signal;=0A= =20=20=0A= Index: testsuite/sim/mips/basic.exp=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/testsuite/sim/mips/basic.exp,v=0A= retrieving revision 1.5=0A= diff -c -3 -p -r1.5 basic.exp=0A= *** testsuite/sim/mips/basic.exp 11 Apr 2004 06:28:08 -0000 1.5=0A= --- testsuite/sim/mips/basic.exp 11 Oct 2005 21:40:21 -0000=0A= *************** if {[istarget mips*-elf] && [board_info=20=0A= *** 71,74 ****=0A= --- 71,76 ----=0A= =20=20=0A= run_sim_test mdmx-ob.s $submodels=0A= run_sim_test mdmx-ob-sb1.s $submodels=0A= +=20=0A= + run_sim_test mips32-dsp.s $models=0A= }=0A= ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: application/octet-stream; name="dsp.igen" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="dsp.igen" Content-length: 49390 // -*- C -*-=0A= =0A= // Simulator definition for the MIPS DSP ASE.=0A= // Copyright (C) 2005 Free Software Foundation, Inc.=0A= // Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.=0A= //=0A= // This file is part of GDB, the GNU debugger.=0A= //=0A= // This program is free software; you can redistribute it and/or modify=0A= // it under the terms of the GNU General Public License as published by=0A= // the Free Software Foundation; either version 2, or (at your option)=0A= // any later version.=0A= //=20=0A= // This program is distributed in the hope that it will be useful,=0A= // but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= // GNU General Public License for more details.=0A= //=20=0A= // You should have received a copy of the GNU General Public License along= =0A= // with this program; if not, write to the Free Software Foundation, Inc.,= =0A= // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= =0A= // op: 0 =3D ADD, 1 =3D SUB=0A= // sat: 0 =3D no saturation, 1 =3D saturation=0A= :function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat=0A= {=0A= int i;=0A= signed32 h0;=0A= signed16 h1, h2;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16, v2 >>=3D 16)=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= if (op =3D=3D 0) // ADD=0A= h0 =3D (signed32)h1 + (signed32)h2;=0A= else // SUB=0A= h0 =3D (signed32)h1 - (signed32)h2;=0A= if (((h0 & 0x10000) >> 1) !=3D (h0 & 0x8000))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= if (sat =3D=3D 1)=0A= {=0A= if (h0 & 0x10000)=0A= h0 =3D 0x8000;=0A= else=0A= h0 =3D 0x7fff;=0A= }=0A= }=0A= result |=3D ((unsigned32)((unsigned16)h0) << i);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= // op: 0 =3D ADD, 1 =3D SUB=0A= :function:::void:do_w_op:int rd, int rs, int rt, int op=0A= {=0A= signed64 h0;=0A= signed32 h1, h2;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= h1 =3D (signed32)v1;=0A= h2 =3D (signed32)v2;=0A= if (op =3D=3D 0) // ADD=0A= h0 =3D (signed64)h1 + (signed64)h2;=0A= else // SUB=0A= h0 =3D (signed64)h1 - (signed64)h2;=0A= if (((h0 & 0x100000000) >> 1) !=3D (h0 & 0x80000000))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= if (h0 & 0x100000000)=0A= h0 =3D 0x80000000;=0A= else=0A= h0 =3D 0x7fffffff;=0A= }=0A= GPR[rd] =3D EXTEND32 (h0);=0A= }=0A= =0A= // op: 0 =3D ADD, 1 =3D SUB=0A= // sat: 0 =3D no saturation, 1 =3D saturation=0A= :function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat=0A= {=0A= int i;=0A= unsigned32 h0;=0A= unsigned8 h1, h2;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= for (i =3D 0; i < 32; i +=3D 8, v1 >>=3D 8, v2 >>=3D 8)=0A= {=0A= h1 =3D (unsigned8)(v1 & 0xff);=0A= h2 =3D (unsigned8)(v2 & 0xff);=0A= if (op =3D=3D 0) // ADD=0A= h0 =3D (unsigned32)h1 + (unsigned32)h2;=0A= else // SUB=0A= h0 =3D (unsigned32)h1 - (unsigned32)h2;=0A= if (h0 & 0x100)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= if (sat =3D=3D 1)=0A= {=0A= if (op =3D=3D 0) // ADD=0A= h0 =3D 0xff;=0A= else // SUB=0A= h0 =3D 0;=0A= }=0A= }=0A= result |=3D ((unsigned32)((unsigned8)h0) << i);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= // op: 0 =3D left, 1 =3D right=0A= :function:::void:do_qb_shift:int rd, int rt, int shift, int op=0A= {=0A= int i, j;=0A= unsigned8 h0;=0A= unsigned32 v1 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= for (i =3D 0; i < 32; i +=3D 8, v1 >>=3D 8)=0A= {=0A= h0 =3D (unsigned8)(v1 & 0xff);=0A= if (op =3D=3D 0) // left=0A= {=0A= for (j =3D 7; j >=3D 8 - shift; j--)=0A= {=0A= if (h0 & (1<> shift;=0A= result |=3D ((unsigned32)h0 << i);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= // op: 0 =3D left, 1 =3D right=0A= // sat: 0 =3D no saturation/rounding, 1 =3D saturation/rounding=0A= :function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat=0A= {=0A= int i, j;=0A= signed16 h0;=0A= unsigned32 v1 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= int setcond;=0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16)=0A= {=0A= h0 =3D (signed16)(v1 & 0xffff);=0A= if (op =3D=3D 0) // left=0A= {=0A= setcond =3D 0;=0A= if (h0 & (1<<15))=0A= {=0A= for (j =3D 14; j >=3D 15 - shift; j--)=0A= {=0A= if (!(h0 & (1 << j)))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= setcond =3D 1;=0A= break;=0A= }=0A= }=0A= }=0A= else=0A= {=0A= for (j =3D 14; j >=3D 15 - shift; j--)=0A= {=0A= if (h0 & (1 << j))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= setcond =3D 2;=0A= break;=0A= }=0A= }=0A= }=0A= h0 =3D h0 << shift;=0A= if (sat =3D=3D 1)=0A= {=0A= if (setcond =3D=3D 2)=0A= h0 =3D 0x7fff;=20=0A= else if (setcond =3D=3D 1)=0A= h0 =3D 0x8000;=0A= }=0A= }=0A= else // right=0A= {=0A= if (sat =3D=3D 1 && shift !=3D 0)=0A= h0 +=3D (1 << (shift - 1));=0A= h0 =3D h0 >> shift;=0A= }=0A= =0A= result |=3D ((unsigned32)((unsigned16)h0) << i);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= :function:::void:do_w_shll:int rd, int rt, int shift=0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[rt];=0A= unsigned32 result =3D 0;=0A= int setcond =3D 0;=0A= if (v1 & (1 << 31))=0A= {=0A= for (i =3D 30; i >=3D 31 - shift; i--)=0A= {=0A= if (!(v1 & (1 << i)))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= setcond =3D 1;=0A= break;=0A= }=0A= }=0A= }=0A= else=0A= {=0A= for (i =3D 30; i >=3D 31 - shift; i--)=0A= {=0A= if (v1 & (1 << i))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= setcond =3D 2;=0A= break;=0A= }=0A= }=0A= }=0A= if (setcond =3D=3D 2)=0A= result =3D 0x7fffffff;=20=0A= else if (setcond =3D=3D 1)=0A= result =3D 0x80000000;=0A= else=0A= result =3D v1 << shift;=20=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= :function:::void:do_w_shra:int rd, int rt, int shift=0A= {=0A= unsigned32 result =3D GPR[rt];=0A= signed32 h0 =3D (signed32)result;=0A= if (shift !=3D 0)=0A= h0 +=3D (1 << (shift - 1));=0A= h0 =3D h0 >> shift;=0A= GPR[rd] =3D EXTEND32 (h0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01010,010000:SPECIAL3:32::ADDQ.PH=0A= "addq.ph r, r, r"=0A= *dsp:=0A= {=0A= do_ph_op (SD_, RD, RS, RT, 0, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01110,010000:SPECIAL3:32::ADDQ_S.PH=0A= "addq_s.ph r, r, r"=0A= *dsp:=0A= {=0A= do_ph_op (SD_, RD, RS, RT, 0, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10110,010000:SPECIAL3:32::ADDQ_S.W=0A= "addq_s.w r, r, r"=0A= *dsp:=0A= {=0A= do_w_op (SD_, RD, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00000,010000:SPECIAL3:32::ADDU.QB=0A= "addu.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_op (SD_, RD, RS, RT, 0, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00100,010000:SPECIAL3:32::ADDU_S.QB=0A= "addu_s.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_op (SD_, RD, RS, RT, 0, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01011,010000:SPECIAL3:32::SUBQ.PH=0A= "subq.ph r, r, r"=0A= *dsp:=0A= {=0A= do_ph_op (SD_, RD, RS, RT, 1, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01111,010000:SPECIAL3:32::SUBQ_S.PH=0A= "subq_s.ph r, r, r"=0A= *dsp:=0A= {=0A= do_ph_op (SD_, RD, RS, RT, 1, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10111,010000:SPECIAL3:32::SUBQ_S.W=0A= "subq_s.w r, r, r"=0A= *dsp:=0A= {=0A= do_w_op (SD_, RD, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00001,010000:SPECIAL3:32::SUBU.QB=0A= "subu.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_op (SD_, RD, RS, RT, 1, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00101,010000:SPECIAL3:32::SUBU_S.QB=0A= "subu_s.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_op (SD_, RD, RS, RT, 1, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10000,010000:SPECIAL3:32::ADDSC=0A= "addsc r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned64 h0;=0A= h0 =3D (unsigned64)v1 + (unsigned64)v2;=0A= if (h0 & 0x100000000LL)=0A= DSPCR |=3D DSPCR_CARRY;=0A= GPR[RD] =3D EXTEND32 (h0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10001,010000:SPECIAL3:32::ADDWC=0A= "addwc r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned64 h0;=0A= signed32 h1 =3D (signed32) v1;=0A= signed32 h2 =3D (signed32) v2;=0A= h0 =3D (signed64)h1 + (signed64)h2=0A= + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);=0A= if (((h0 & 0x100000000LL) >> 1) !=3D (h0 & 0x80000000))=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= GPR[RD] =3D EXTEND32 (h0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10010,010000:SPECIAL3:32::MODSUB=0A= "modsub r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 result =3D 0;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned32 decr =3D v2 & 0xff;=0A= unsigned32 lastindex =3D (v2 & 0xffff00) >> 8;=0A= if (v1 =3D=3D 0)=0A= result =3D lastindex;=0A= else=0A= result =3D v1 - decr;=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.RS,00000,5.RD,10100,010000:SPECIAL3:32::RADDU.W.QB=0A= "raddu.w.qb r, r"=0A= *dsp:=0A= {=0A= int i;=0A= unsigned8 h0;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 result =3D 0;=0A= for (i =3D 0; i < 32; i +=3D 8, v1 >>=3D 8)=0A= {=0A= h0 =3D (unsigned8)(v1 & 0xff);=0A= result +=3D (unsigned32)h0;=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,01001,010010:SPECIAL3:32::ABSQ_S.PH=0A= "absq_s.ph r, r"=0A= *dsp:=0A= {=0A= int i;=0A= signed16 h0;=0A= unsigned32 v1 =3D GPR[RT];=0A= unsigned32 result =3D 0;=0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16)=0A= {=0A= h0 =3D (signed16)(v1 & 0xffff);=0A= if (h0 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= h0 =3D 0x7fff;=0A= }=0A= else if (h0 & 0x8000)=0A= h0 =3D -h0;=20=0A= result |=3D ((unsigned32)((unsigned16)h0) << i);=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,10001,010010:SPECIAL3:32::ABSQ_S.W=0A= "absq_s.w r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= signed32 h0 =3D (signed32)v1;=0A= if (h0 =3D=3D (signed32)0x80000000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG4;=0A= h0 =3D 0x7fffffff;=0A= }=0A= else if (h0 & 0x80000000)=0A= h0 =3D -h0;=20=0A= GPR[RD] =3D EXTEND32 (h0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01100,010001:SPECIAL3:32::PRECRQ.QB.PH=0A= "precrq.qb.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned32 tempu =3D (v1 & 0xff000000) >> 24;=0A= unsigned32 tempv =3D (v1 & 0xff00) >> 8;=0A= unsigned32 tempw =3D (v2 & 0xff000000) >> 24;=0A= unsigned32 tempx =3D (v2 & 0xff00) >> 8;=0A= GPR[RD] =3D EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | temp= x);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10100,010001:SPECIAL3:32::PRECRQ.PH.W=0A= "precrq.ph.w r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned32 tempu =3D (v1 & 0xffff0000) >> 16;=0A= unsigned32 tempv =3D (v2 & 0xffff0000) >> 16;=0A= GPR[RD] =3D EXTEND32 ((tempu << 16) | tempv);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10101,010001:SPECIAL3:32::PRECRQ_RS.PH.W=0A= "precrq_rs.ph.w r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= signed32 h1 =3D (signed32)v1;=0A= signed32 h2 =3D (signed32)v2;=0A= signed64 temp1 =3D (signed64)h1 + (signed64)0x8000;=0A= signed32 temp2;=0A= signed64 temp3 =3D (signed64)h2 + (signed64)0x8000;=0A= signed32 temp4;=0A= if (((temp1 & 0x100000000LL) >> 1) !=3D (temp1 & 0x80000000))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= temp2 =3D 0x7fff;=0A= }=0A= else=0A= temp2 =3D (signed32)((temp1 & 0xffff0000) >> 16);=0A= if (((temp3 & 0x100000000LL) >> 1) !=3D (temp3 & 0x80000000))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= temp4 =3D 0x7fff;=0A= }=0A= else=0A= temp4 =3D (signed32)((temp3 & 0xffff0000) >> 16);=0A= GPR[RD] =3D EXTEND32 ((temp2 << 16) | temp4);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01111,010001:SPECIAL3:32::PRECRQU_S.QB.PH=0A= "precrqu_s.qb.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned32 tempu, tempv, tempw, tempx;=0A= if (v1 & 0x80000000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempu =3D 0;=0A= }=0A= else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempu =3D 0xff;=0A= }=0A= else=0A= tempu =3D (v1 & 0x7f800000) >> 23;=0A= if (v1 & 0x8000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempv =3D 0;=0A= }=0A= else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempv =3D 0xff;=0A= }=0A= else=0A= tempv =3D (v1 & 0x7f80) >> 7;=0A= if (v2 & 0x80000000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempw =3D 0;=0A= }=0A= else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempw =3D 0xff;=0A= }=0A= else=0A= tempw =3D (v2 & 0x7f800000) >> 23;=0A= if (v2 & 0x8000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempx =3D 0;=0A= }=0A= else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG6;=0A= tempx =3D 0xff;=0A= }=0A= else=0A= tempx =3D (v2 & 0x7f80) >> 7;=0A= GPR[RD] =3D EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | temp= x);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,01100,010010:SPECIAL3:32::PRECEQ.W.PHL=0A= "preceq.w.phl r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 (v1 & 0xffff0000);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,01101,010010:SPECIAL3:32::PRECEQ.W.PHR=0A= "preceq.w.phr r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xffff) << 16);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,00100,010010:SPECIAL3:32::PRECEQU.PH.QBL=0A= "precequ.ph.qbl r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff0000) >> 9);= =0A= }=0A= =0A= 011111,00000,5.RT,5.RD,00101,010010:SPECIAL3:32::PRECEQU.PH.QBR=0A= "precequ.ph.qbr r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,00110,010010:SPECIAL3:32::PRECEQU.PH.QBLA=0A= "precequ.ph.qbla r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff00) >> 1);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,00111,010010:SPECIAL3:32::PRECEQU.PH.QBRA=0A= "precequ.ph.qbra r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff0000) << 7) | ((v1 & 0xff) << 7);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,11100,010010:SPECIAL3:32::PRECEU.PH.QBL=0A= "preceu.ph.qbl r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff0000) >> 16);= =0A= }=0A= =0A= 011111,00000,5.RT,5.RD,11101,010010:SPECIAL3:32::PRECEU.PH.QBR=0A= "preceu.ph.qbr r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,11110,010010:SPECIAL3:32::PRECEU.PH.QBLA=0A= "preceu.ph.qbla r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff00) >> 8);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,11111,010010:SPECIAL3:32::PRECEU.PH.QBRA=0A= "preceu.ph.qbra r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 & 0xff0000) | (v1 & 0xff));=0A= }=0A= =0A= 011111,00,3.SHIFT3,5.RT,5.RD,00000,010011:SPECIAL3:32::SHLL.QB=0A= "shll.qb r, r, "=0A= *dsp:=0A= {=0A= do_qb_shift (SD_, RD, RT, SHIFT3, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00010,010011:SPECIAL3:32::SHLLV.QB=0A= "shllv.qb r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x7;=0A= do_qb_shift (SD_, RD, RT, shift, 0);=0A= }=0A= =0A= 011111,0,4.SHIFT4,5.RT,5.RD,01000,010011:SPECIAL3:32::SHLL.PH=0A= "shll.ph r, r, "=0A= *dsp:=0A= {=0A= do_ph_shift (SD_, RD, RT, SHIFT4, 0, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01010,010011:SPECIAL3:32::SHLLV.PH=0A= "shllv.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0xf;=0A= do_ph_shift (SD_, RD, RT, shift, 0, 0);=0A= }=0A= =0A= 011111,0,4.SHIFT4,5.RT,5.RD,01100,010011:SPECIAL3:32::SHLL_S.PH=0A= "shll_s.ph r, r, "=0A= *dsp:=0A= {=0A= do_ph_shift (SD_, RD, RT, SHIFT4, 0, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01110,010011:SPECIAL3:32::SHLLV_S.PH=0A= "shllv_s.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0xf;=0A= do_ph_shift (SD_, RD, RT, shift, 0, 1);=0A= }=0A= =0A= 011111,5.SHIFT5,5.RT,5.RD,10100,010011:SPECIAL3:32::SHLL_S.W=0A= "shll_s.w r, r, "=0A= *dsp:=0A= {=0A= do_w_shll (SD_, RD, RT, SHIFT5);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10110,010011:SPECIAL3:32::SHLLV_S.W=0A= "shllv_s.w r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_w_shll (SD_, RD, RT, shift);=0A= }=0A= =0A= 011111,00,3.SHIFT3,5.RT,5.RD,00001,010011:SPECIAL3:32::SHRL.QB=0A= "shrl.qb r, r, "=0A= *dsp:=0A= {=0A= do_qb_shift (SD_, RD, RT, SHIFT3, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00011,010011:SPECIAL3:32::SHRLV.QB=0A= "shrlv.qb r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x7;=0A= do_qb_shift (SD_, RD, RT, shift, 1);=0A= }=0A= =0A= 011111,0,4.SHIFT4,5.RT,5.RD,01001,010011:SPECIAL3:32::SHRA.PH=0A= "shra.ph r, r, "=0A= *dsp:=0A= {=0A= do_ph_shift (SD_, RD, RT, SHIFT4, 1, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01011,010011:SPECIAL3:32::SHRAV.PH=0A= "shrav.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0xf;=0A= do_ph_shift (SD_, RD, RT, shift, 1, 0);=0A= }=0A= =0A= 011111,0,4.SHIFT4,5.RT,5.RD,01101,010011:SPECIAL3:32::SHRA_R.PH=0A= "shra_r.ph r, r, "=0A= *dsp:=0A= {=0A= do_ph_shift (SD_, RD, RT, SHIFT4, 1, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01111,010011:SPECIAL3:32::SHRAV_R.PH=0A= "shrav_r.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0xf;=0A= do_ph_shift (SD_, RD, RT, shift, 1, 1);=0A= }=0A= =0A= 011111,5.SHIFT5,5.RT,5.RD,10101,010011:SPECIAL3:32::SHRA_R.W=0A= "shra_r.w r, r, "=0A= *dsp:=0A= {=0A= do_w_shra (SD_, RD, RT, SHIFT5);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,10111,010011:SPECIAL3:32::SHRAV_R.W=0A= "shrav_r.w r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_w_shra (SD_, RD, RT, shift);=0A= }=0A= =0A= // loc: 0 =3D qhl, 1 =3D qhr=0A= :function:::void:do_qb_muleu:int rd, int rs, int rt, int loc=0A= {=0A= int i;=0A= unsigned32 result =3D 0;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned16 h1, h2;=0A= unsigned32 prod;=0A= if (loc =3D=3D 0)=0A= v1 >>=3D 16;=0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 8, v2 >>=3D 16)=0A= {=0A= h1 =3D (unsigned16)(v1 & 0xff);=0A= h2 =3D (unsigned16)(v2 & 0xffff);=0A= prod =3D (unsigned32)h1 * (unsigned32)h2;=0A= if (prod > 0xffff)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG5;=0A= prod =3D 0xffff;=0A= }=0A= result |=3D ((unsigned32)prod << i);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00110,010000:SPECIAL3:32::MULEU_S.PH.QBL=0A= "muleu_s.ph.qbl r, r, r"=0A= *dsp:=0A= {=0A= do_qb_muleu (SD_, RD, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00111,010000:SPECIAL3:32::MULEU_S.PH.QBR=0A= "muleu_s.ph.qbr r, r, r"=0A= *dsp:=0A= {=0A= do_qb_muleu (SD_, RD, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH=0A= "mulq_rs.ph r, r, r"=0A= *dsp:=0A= {=0A= int i;=0A= unsigned32 result =3D 0;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= signed16 h1, h2;=0A= signed32 prod;=0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16, v2 >>=3D 16)=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= if (h1 =3D=3D (signed16)0x8000 && h2 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG5;=0A= prod =3D 0x7fffffff;=0A= }=0A= else=0A= prod =3D (((signed32)h1 * (signed32)h2) << 1) + (signed32)0x8000;=0A= =0A= result |=3D (((unsigned32)prod >> 16) << i);=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= // loc: 0 =3D phl, 1 =3D phr=0A= :function:::void:do_ph_muleq:int rd, int rs, int rt, int loc=0A= {=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= signed16 h1, h2;=0A= signed32 prod;=0A= if (loc =3D=3D 0)=0A= {=0A= h1 =3D (signed16)(v1 >> 16);=0A= h2 =3D (signed16)(v2 >> 16);=0A= }=0A= else=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= }=0A= if (h1 =3D=3D (signed16)0x8000 && h2 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG5;=0A= prod =3D 0x7fffffff;=0A= }=0A= else=0A= prod =3D ((signed32)h1 * (signed32)h2) << 1;=0A= GPR[rd] =3D EXTEND32 (prod);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,11100,010000:SPECIAL3:32::MULEQ_S.W.PHL=0A= "muleq_s.w.phl r, r, r"=0A= *dsp:=0A= {=0A= do_ph_muleq (SD_, RD, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,11101,010000:SPECIAL3:32::MULEQ_S.W.PHR=0A= "muleq_s.w.phr r, r, r"=0A= *dsp:=0A= {=0A= do_ph_muleq (SD_, RD, RS, RT, 1);=0A= }=0A= =0A= // op: 0 =3D DPAU 1 =3D DPSU=0A= // loc: 0 =3D qbl, 1 =3D qbr=0A= :function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc= =0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned8 h1, h2;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned64 prod =3D (((unsigned64)hi) << 32) + (unsigned64)lo;=0A= if (loc =3D=3D 0)=0A= {=0A= v1 >>=3D 16;=0A= v2 >>=3D 16;=0A= }=0A= for (i =3D 0; i < 16; i +=3D 8, v1 >>=3D 8, v2 >>=3D 8)=0A= {=0A= h1 =3D (unsigned8)(v1 & 0xff);=0A= h2 =3D (unsigned8)(v2 & 0xff);=0A= if (op =3D=3D 0) // DPAU=0A= prod +=3D (unsigned64)h1 * (unsigned64)h2;=0A= else // DPSU=0A= prod -=3D (unsigned64)h1 * (unsigned64)h2;=0A= }=0A= DSPLO(ac) =3D EXTEND32 (prod);=0A= DSPHI(ac) =3D EXTEND32 (prod >> 32);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00011,110000:SPECIAL3:32::DPAU.H.QBL=0A= "dpau.h.qbl ac, r, r"=0A= *dsp:=0A= {=0A= do_qb_dot_product (SD_, AC, RS, RT, 0, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00111,110000:SPECIAL3:32::DPAU.H.QBR=0A= "dpau.h.qbr ac, r, r"=0A= *dsp:=0A= {=0A= do_qb_dot_product (SD_, AC, RS, RT, 0, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01011,110000:SPECIAL3:32::DPSU.H.QBL=0A= "dpsu.h.qbl ac, r, r"=0A= *dsp:=0A= {=0A= do_qb_dot_product (SD_, AC, RS, RT, 1, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01111,110000:SPECIAL3:32::DPSU.H.QBR=0A= "dpsu.h.qbr ac, r, r"=0A= *dsp:=0A= {=0A= do_qb_dot_product (SD_, AC, RS, RT, 1, 1);=0A= }=0A= =0A= // op: 0 =3D DPAQ 1 =3D DPSQ=0A= :function:::void:do_ph_dot_product:int ac, int rs, int rt, int op=0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= signed16 h1, h2;=0A= signed32 result;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= signed64 prod =3D (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);= =0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16, v2 >>=3D 16)=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= if (h1 =3D=3D (signed16)0x8000 && h2 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= result =3D (signed32)0x7fffffff;=0A= }=0A= else=0A= result =3D ((signed32)h1 * (signed32)h2) << 1;=0A= =0A= if (op =3D=3D 0) // DPAQ=0A= prod +=3D (signed64)result;=0A= else // DPSQ=0A= prod -=3D (signed64)result;=0A= }=0A= DSPLO(ac) =3D EXTEND32 (prod);=0A= DSPHI(ac) =3D EXTEND32 (prod >> 32);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00100,110000:SPECIAL3:32::DPAQ_S.W.PH=0A= "dpaq_s.w.ph ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_dot_product (SD_, AC, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00101,110000:SPECIAL3:32::DPSQ_S.W.PH=0A= "dpsq_s.w.ph ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_dot_product (SD_, AC, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00110,110000:SPECIAL3:32::MULSAQ_S.W.PH=0A= "mulsaq_s.w.ph ac, r, r"=0A= *dsp:=0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= signed16 h1, h2;=0A= signed32 result;=0A= unsigned32 lo =3D DSPLO(AC);=0A= unsigned32 hi =3D DSPHI(AC);=0A= signed64 prod =3D (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);= =0A= for (i =3D 0; i < 32; i +=3D 16, v1 >>=3D 16, v2 >>=3D 16)=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= if (h1 =3D=3D (signed16)0x8000 && h2 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + AC));=0A= result =3D (signed32) 0x7fffffff;=0A= }=0A= else=0A= result =3D ((signed32)h1 * (signed32)h2) << 1;=0A= =0A= if (i =3D=3D 0)=0A= prod -=3D (signed64) result;=0A= else=0A= prod +=3D (signed64) result;=0A= }=0A= DSPLO(AC) =3D EXTEND32 (prod);=0A= DSPHI(AC) =3D EXTEND32 (prod >> 32);=0A= }=0A= =0A= // op: 0 =3D DPAQ 1 =3D DPSQ=0A= :function:::void:do_w_dot_product:int ac, int rs, int rt, int op=0A= {=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= signed32 h1, h2;=0A= signed64 result;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned32 resultlo;=0A= unsigned32 resulthi;=0A= unsigned32 carry;=0A= unsigned64 temp1;=0A= signed64 temp2;=0A= h1 =3D (signed32) v1;=0A= h2 =3D (signed32) v2;=0A= if (h1 =3D=3D 0x80000000 && h2 =3D=3D 0x80000000)=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= result =3D (signed64) 0x7fffffffffffffffLL;=0A= }=0A= else=0A= result =3D ((signed64)h1 * (signed64)h2) << 1;=0A= resultlo =3D (unsigned32)(result);=0A= resulthi =3D (unsigned32)(result >> 32);=0A= if (op =3D=3D0) // DPAQ=0A= {=0A= temp1 =3D (unsigned64)lo + (unsigned64)resultlo;=0A= carry =3D (unsigned32)((temp1 >> 32) & 1);=0A= temp2 =3D (signed64)((signed32)hi) + (signed64)((signed32)resulthi) += =0A= (signed64)((signed32)carry);=0A= }=0A= else // DPSQ=0A= {=0A= temp1 =3D (unsigned64)lo - (unsigned64)resultlo;=0A= carry =3D (unsigned32)((temp1 >> 32) & 1);=0A= temp2 =3D (signed64)((signed32)hi) - (signed64)((signed32)resulthi) -= =0A= (signed64)((signed32)carry);=0A= }=0A= if (((temp2 & 0x100000000LL) >> 1) !=3D (temp2 & 0x80000000LL))=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= if (temp2 & 0x100000000LL)=0A= {=0A= DSPLO(ac) =3D EXTEND32 (0x00000000);=0A= DSPHI(ac) =3D EXTEND32 (0x80000000);=0A= }=0A= else=0A= {=0A= DSPLO(ac) =3D EXTEND32 (0xffffffff);=0A= DSPHI(ac) =3D EXTEND32 (0x7fffffff);=0A= }=0A= }=0A= else=0A= {=0A= DSPLO(ac) =3D EXTEND32 (temp1);=0A= DSPHI(ac) =3D EXTEND32 (temp2);=0A= }=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01100,110000:SPECIAL3:32::DPAQ_SA.L.W=0A= "dpaq_sa.l.w ac, r, r"=0A= *dsp:=0A= {=0A= do_w_dot_product (SD_, AC, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01101,110000:SPECIAL3:32::DPSQ_SA.L.W=0A= "dpsq_sa.l.w ac, r, r"=0A= *dsp:=0A= {=0A= do_w_dot_product (SD_, AC, RS, RT, 1);=0A= }=0A= =0A= // op: 0 =3D MAQ_S 1 =3D MAQ_SA=0A= // loc: 0 =3D phl, 1 =3D phr=0A= :function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc=0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= signed16 h1, h2;=0A= signed32 result;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= signed64 prod =3D (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);= =0A= if (loc =3D=3D 0)=0A= {=0A= h1 =3D (signed16)(v1 >> 16);=0A= h2 =3D (signed16)(v2 >> 16);=0A= }=0A= else=0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= }=0A= if (h1 =3D=3D (signed16)0x8000 && h2 =3D=3D (signed16)0x8000)=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= result =3D (signed32)0x7fffffff;=0A= }=0A= else=0A= result =3D ((signed32)h1 * (signed32)h2) << 1;=0A= prod +=3D (signed64)result;=0A= if (op =3D=3D 1) // MAQ_SA=0A= {=0A= if (prod & 0x8000000000000000LL)=0A= {=0A= for (i =3D 62; i >=3D 31; i--)=0A= {=0A= if (!(prod & ((signed64)1 << i)))=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= prod =3D 0xffffffff80000000LL;=0A= break;=0A= }=0A= }=0A= }=0A= else=0A= {=0A= for (i =3D 62; i >=3D 31; i--)=0A= {=0A= if (prod & ((signed64)1 << i))=0A= {=0A= DSPCR |=3D (1 << (DSPCR_OUFLAG_SHIFT + ac));=0A= prod =3D 0x7fffffff;=0A= break;=0A= }=0A= }=0A= }=0A= }=0A= DSPLO(ac) =3D EXTEND32 (prod);=0A= DSPHI(ac) =3D EXTEND32 (prod >> 32);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,10100,110000:SPECIAL3:32::MAQ_S.W.PHL=0A= "maq_s.w.phl ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_maq (SD_, AC, RS, RT, 0, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,10110,110000:SPECIAL3:32::MAQ_S.W.PHR=0A= "maq_s.w.phr ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_maq (SD_, AC, RS, RT, 0, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,10000,110000:SPECIAL3:32::MAQ_SA.W.PHL=0A= "maq_sa.w.phl ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_maq (SD_, AC, RS, RT, 1, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,10010,110000:SPECIAL3:32::MAQ_SA.W.PHR=0A= "maq_sa.w.phr ac, r, r"=0A= *dsp:=0A= {=0A= do_ph_maq (SD_, AC, RS, RT, 1, 1);=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,11011,010010:SPECIAL3:32::BITREV=0A= "bitrev r, r"=0A= *dsp:=0A= {=0A= int i;=0A= unsigned32 v1 =3D GPR[RT];=0A= unsigned32 h1 =3D 0;=0A= for (i =3D 0; i < 16; i++)=0A= {=0A= if (v1 & (1 << i))=0A= h1 |=3D (1 << (15 - i));=0A= }=0A= GPR[RD] =3D EXTEND32 (h1);=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,00000,001100:SPECIAL3:32::INSV=0A= "insv r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned32 pos =3D (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;=0A= unsigned32 size =3D (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;=0A= unsigned32 mask1, mask2, mask3, result;=0A= if (size < 32)=0A= mask1 =3D (1 << size) - 1;=0A= else=0A= mask1 =3D 0xffffffff;=0A= mask2 =3D (1 << pos) - 1;=0A= if (pos + size < 32)=0A= mask3 =3D ~((1 << (pos + size)) - 1);=0A= else=0A= mask3 =3D 0;=0A= result =3D (v2 & mask3) | ((v1 & mask1) << pos) | (v2 & mask2);=0A= GPR[RT] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,00,8.IMM8,5.RD,00010,010010:SPECIAL3:32::REPL.QB=0A= "repl.qb r, "=0A= *dsp:=0A= {=0A= GPR[RD] =3D EXTEND32 ((IMM8 << 24) | (IMM8 << 16) | (IMM8 << 8) | IMM8);= =0A= }=0A= =0A= 011111,00000,5.RT,5.RD,00011,010010:SPECIAL3:32::REPLV.QB=0A= "replv.qb r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= v1 =3D v1 & 0xff;=0A= GPR[RD] =3D EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1);=0A= }=0A= =0A= 011111,10.IMM10,5.RD,01010,010010:SPECIAL3:32::REPL.PH=0A= "repl.ph r, "=0A= *dsp:=0A= {=0A= signed32 v1 =3D IMM10;=0A= if (v1 & 0x200)=0A= v1 |=3D 0xfffffc00;=0A= GPR[RD] =3D EXTEND32 ((v1 << 16) | (v1 & 0xffff));=0A= }=0A= =0A= 011111,00000,5.RT,5.RD,01011,010010:SPECIAL3:32::REPLV.PH=0A= "replv.ph r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RT];=0A= v1 =3D v1 & 0xffff;=0A= GPR[RD] =3D EXTEND32 ((v1 << 16) | v1);=0A= }=0A= =0A= // op: 0 =3D EQ, 1 =3D LT, 2 =3D LE=0A= :function:::void:do_qb_cmpu:int rs, int rt, int op=0A= {=0A= int i, j;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned8 h1, h2;=0A= unsigned32 mask;=0A= for (i =3D 0, j =3D 0; i < 32; i +=3D 8, j++, v1 >>=3D 8, v2 >>=3D 8)=0A= {=0A= h1 =3D (unsigned8)(v1 & 0xff);=0A= h2 =3D (unsigned8)(v2 & 0xff);=0A= mask =3D ~(1 << (DSPCR_CCOND_SHIFT + j));=0A= DSPCR &=3D mask;=0A= if (op =3D=3D 0) // EQ=0A= DSPCR |=3D ((h1 =3D=3D h2) << (DSPCR_CCOND_SHIFT + j));=0A= else if (op =3D=3D 1) // LT=0A= DSPCR |=3D ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));=0A= else // LE=0A= DSPCR |=3D ((h1 <=3D h2) << (DSPCR_CCOND_SHIFT + j));=0A= }=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,00000,010001:SPECIAL3:32::CMPU.EQ.QB=0A= "cmpu.eq.qb r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpu (SD_, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,00001,010001:SPECIAL3:32::CMPU.LT.QB=0A= "cmpu.lt.qb r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpu (SD_, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,00010,010001:SPECIAL3:32::CMPU.LE.QB=0A= "cmpu.le.qb r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpu (SD_, RS, RT, 2);=0A= }=0A= =0A= // op: 0 =3D EQ, 1 =3D LT, 2 =3D LE=0A= :function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op=0A= {=0A= int i, j;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= unsigned8 h1, h2;=0A= unsigned32 result =3D 0;=0A= for (i =3D 0, j =3D 0; i < 32; i +=3D 8, j++, v1 >>=3D 8, v2 >>=3D 8)=0A= {=0A= h1 =3D (unsigned8)(v1 & 0xff);=0A= h2 =3D (unsigned8)(v2 & 0xff);=0A= if (op =3D=3D 0) // EQ=0A= result |=3D ((h1 =3D=3D h2) << j);=0A= else if (op =3D=3D 1) // LT=0A= result |=3D ((h1 < h2) << j);=0A= else // LE=0A= result |=3D ((h1 <=3D h2) << j);=0A= }=0A= GPR[rd] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00100,010001:SPECIAL3:32::CMPGU.EQ.QB=0A= "cmpgu.eq.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpgu (SD_, RD, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00101,010001:SPECIAL3:32::CMPGU.LT.QB=0A= "cmpgu.lt.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpgu (SD_, RD, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00110,010001:SPECIAL3:32::CMPGU.LE.QB=0A= "cmpgu.le.qb r, r, r"=0A= *dsp:=0A= {=0A= do_qb_cmpgu (SD_, RD, RS, RT, 2);=0A= }=0A= =0A= // op: 0 =3D EQ, 1 =3D LT, 2 =3D LE=0A= :function:::void:do_ph_cmpu:int rs, int rt, int op=0A= {=0A= int i, j;=0A= unsigned32 v1 =3D GPR[rs];=0A= unsigned32 v2 =3D GPR[rt];=0A= signed16 h1, h2;=0A= unsigned32 mask;=0A= for (i =3D 0, j =3D 0; i < 32; i +=3D 16, j++, v1 >>=3D 16, v2 >>=3D 16)= =0A= {=0A= h1 =3D (signed16)(v1 & 0xffff);=0A= h2 =3D (signed16)(v2 & 0xffff);=0A= mask =3D ~(1 << (DSPCR_CCOND_SHIFT + j));=0A= DSPCR &=3D mask;=0A= if (op =3D=3D 0) // EQ=0A= DSPCR |=3D ((h1 =3D=3D h2) << (DSPCR_CCOND_SHIFT + j));=0A= else if (op =3D=3D 1) // LT=0A= DSPCR |=3D ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));=0A= else // LE=0A= DSPCR |=3D ((h1 <=3D h2) << (DSPCR_CCOND_SHIFT + j));=0A= }=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,01000,010001:SPECIAL3:32::CMP.EQ.PH=0A= "cmp.eq.ph r, r"=0A= *dsp:=0A= {=0A= do_ph_cmpu (SD_, RS, RT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,01001,010001:SPECIAL3:32::CMP.LT.PH=0A= "cmp.lt.ph r, r"=0A= *dsp:=0A= {=0A= do_ph_cmpu (SD_, RS, RT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,00000,01010,010001:SPECIAL3:32::CMP.LE.PH=0A= "cmp.le.ph r, r"=0A= *dsp:=0A= {=0A= do_ph_cmpu (SD_, RS, RT, 2);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,00011,010001:SPECIAL3:32::PICK.QB=0A= "pick.qb r, r, r"=0A= *dsp:=0A= {=0A= int i, j;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned8 h1, h2;=0A= unsigned32 result =3D 0;=0A= for (i =3D 0, j =3D 0; i < 32; i +=3D 8, j++, v1 >>=3D 8, v2 >>=3D 8)=0A= {=0A= h1 =3D (unsigned8)(v1 & 0xff);=0A= h2 =3D (unsigned8)(v2 & 0xff);=0A= if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))=0A= result |=3D (unsigned32)(h1 << i);=0A= else=0A= result |=3D (unsigned32)(h2 << i);=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01011,010001:SPECIAL3:32::PICK.PH=0A= "pick.ph r, r, r"=0A= *dsp:=0A= {=0A= int i, j;=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= unsigned16 h1, h2;=0A= unsigned32 result =3D 0;=0A= for (i =3D 0, j =3D 0; i < 32; i +=3D 16, j++, v1 >>=3D 16, v2 >>=3D 16)= =0A= {=0A= h1 =3D (unsigned16)(v1 & 0xffff);=0A= h2 =3D (unsigned16)(v2 & 0xffff);=0A= if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))=0A= result |=3D (unsigned32)(h1 << i);=0A= else=0A= result |=3D (unsigned32)(h2 << i);=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.RS,5.RT,5.RD,01110,010001:SPECIAL3:32::PACKRL.PH=0A= "packrl.ph r, r, r"=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= unsigned32 v2 =3D GPR[RT];=0A= GPR[RD] =3D EXTEND32 ((v1 << 16) + (v2 >> 16));=0A= }=0A= =0A= // op: 0 =3D EXTR, 1 =3D EXTR_R, 2 =3D EXTR_RS=0A= :function:::void:do_w_extr:int rt, int ac, int shift, int op=0A= {=0A= int i;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned64 prod =3D (((unsigned64)hi) << 32) + (unsigned64)lo;=0A= signed64 result =3D (signed64)prod;=0A= int setcond =3D 0;=0A= if (!(prod & 0x8000000000000000LL))=0A= {=0A= for (i =3D 62; i >=3D (shift + 31); i--)=0A= {=0A= if (prod & ((unsigned64)1 << i))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG7;=0A= setcond =3D 1;=0A= break;=0A= }=0A= }=0A= if (((prod >> (shift - 1)) & 0xffffffffLL) =3D=3D 0xffffffffLL)=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG7;=0A= setcond =3D 1;=0A= }=0A= }=0A= else=0A= {=0A= for (i =3D 62; i >=3D (shift + 31); i--)=0A= {=0A= if (!(prod & ((unsigned64)1 << i)))=0A= {=0A= DSPCR |=3D DSPCR_OUFLAG7;=0A= setcond =3D 2;=0A= break;=0A= }=0A= }=0A= }=0A= if (op =3D=3D 0) // EXTR=0A= result =3D result >> shift;=0A= else if (op =3D=3D 1) // EXTR_R=0A= {=0A= if (shift !=3D 0)=0A= result =3D ((result >> (shift - 1)) + 1) >> 1;=0A= else=0A= result =3D result >> shift;=0A= }=0A= else // EXTR_RS=0A= {=0A= if (setcond =3D=3D 1)=0A= result =3D 0x7fffffff;=0A= else if (setcond =3D=3D 2)=0A= result =3D 0x80000000;=0A= else=20=0A= {=0A= if (shift !=3D 0)=0A= result =3D ((result >> (shift - 1)) + 1) >> 1;=0A= else=0A= result =3D result >> shift;=0A= }=0A= }=0A= GPR[rt] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.SHIFT,5.RT,000,2.AC,00000,111000:SPECIAL3:32::EXTR.W=0A= "extr.w r, ac, "=0A= *dsp:=0A= {=0A= do_w_extr (SD_, RT, AC, SHIFT, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00001,111000:SPECIAL3:32::EXTRV.W=0A= "extrv.w r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_w_extr (SD_, RT, AC, shift, 0);=0A= }=0A= =0A= 011111,5.SHIFT,5.RT,000,2.AC,00100,111000:SPECIAL3:32::EXTR_R.W=0A= "extr_r.w r, ac, "=0A= *dsp:=0A= {=0A= do_w_extr (SD_, RT, AC, SHIFT, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00101,111000:SPECIAL3:32::EXTRV_R.W=0A= "extrv_r.w r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_w_extr (SD_, RT, AC, shift, 1);=0A= }=0A= =0A= 011111,5.SHIFT,5.RT,000,2.AC,00110,111000:SPECIAL3:32::EXTR_RS.W=0A= "extr_rs.w r, ac, "=0A= *dsp:=0A= {=0A= do_w_extr (SD_, RT, AC, SHIFT, 2);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00111,111000:SPECIAL3:32::EXTRV_RS.W=0A= "extrv_rs.w r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_w_extr (SD_, RT, AC, shift, 2);=0A= }=0A= =0A= :function:::void:do_h_extr:int rt, int ac, int shift=0A= {=0A= int i;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned64 prod =3D (((unsigned64)hi) << 32) + (unsigned64)lo;=0A= signed64 result =3D (signed64)prod;=0A= signed64 value =3D 0xffffffffffff8000LL;=0A= result >>=3D shift;=0A= if (result > 0x7fff)=0A= {=0A= result =3D 0x7fff;=0A= DSPCR |=3D DSPCR_OUFLAG7;=0A= }=0A= else if (result < value)=0A= {=0A= result =3D value;=0A= DSPCR |=3D DSPCR_OUFLAG7;=0A= }=0A= GPR[rt] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.SHIFT,5.RT,000,2.AC,01110,111000:SPECIAL3:32::EXTR_S.H=0A= "extr_s.h r, ac, "=0A= *dsp:=0A= {=0A= do_h_extr (SD_, RT, AC, SHIFT);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01111,111000:SPECIAL3:32::EXTRV_S.H=0A= "extrv_s.h r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 shift =3D GPR[RS] & 0x1f;=0A= do_h_extr (SD_, RT, AC, shift);=0A= }=0A= =0A= // op: 0 =3D EXTP, 1 =3D EXTPDP=0A= :function:::void:do_extp:int rt, int ac, int size, int op=0A= {=0A= signed32 pos =3D (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned64 prod =3D (((unsigned64)hi) << 32) + (unsigned64)lo;=0A= unsigned64 result =3D 0;=0A= if (pos - (size + 1) >=3D -1)=0A= {=0A= prod >>=3D (pos - size);=0A= result =3D prod & (((unsigned64)1 << (size + 1)) - 1);=0A= DSPCR &=3D (~DSPCR_EFI_SMASK);=0A= if (op =3D=3D 1) // EXTPDP=0A= {=0A= if (pos - (size + 1) >=3D 0)=0A= {=0A= DSPCR &=3D (~DSPCR_POS_SMASK);=0A= DSPCR |=3D ((pos - (size + 1)) & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;= =0A= }=0A= else if (pos - (size + 1) =3D=3D -1)=0A= {=0A= DSPCR |=3D DSPCR_POS_SMASK;=0A= }=0A= }=0A= }=0A= else=0A= {=0A= DSPCR |=3D DSPCR_EFI;=0A= Unpredictable ();=0A= }=0A= GPR[rt] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.SIZE,5.RT,000,2.AC,00010,111000:SPECIAL3:32::EXTP=0A= "extp r, ac, "=0A= *dsp:=0A= {=0A= do_extp (SD_, RT, AC, SIZE, 0);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,00011,111000:SPECIAL3:32::EXTPV=0A= "extpv r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 size =3D GPR[RS] & 0x1f;=0A= do_extp (SD_, RT, AC, size, 0);=0A= }=0A= =0A= 011111,5.SIZE,5.RT,000,2.AC,01010,111000:SPECIAL3:32::EXTPDP=0A= "extpdp r, ac, "=0A= *dsp:=0A= {=0A= do_extp (SD_, RT, AC, SIZE, 1);=0A= }=0A= =0A= 011111,5.RS,5.RT,000,2.AC,01011,111000:SPECIAL3:32::EXTPDPV=0A= "extpdpv r, ac, r"=0A= *dsp:=0A= {=0A= unsigned32 size =3D GPR[RS] & 0x1f;=0A= do_extp (SD_, RT, AC, size, 1);=0A= }=0A= =0A= :function:::void:do_shilo:int ac, int shift=0A= {=0A= unsigned32 lo =3D DSPLO(ac);=0A= unsigned32 hi =3D DSPHI(ac);=0A= unsigned64 prod =3D (((unsigned64)hi) << 32) + (unsigned64)lo;=0A= if (shift > 31)=0A= shift =3D shift - 64;=0A= if (shift >=3D 0)=0A= prod >>=3D shift;=0A= else=0A= prod <<=3D (-shift);=0A= DSPLO(ac) =3D EXTEND32 (prod);=0A= DSPHI(ac) =3D EXTEND32 (prod >> 32);=0A= }=0A= =0A= 011111,6.SHIFT6,0000,000,2.AC,11010,111000:SPECIAL3:32::SHILO=0A= "shilo ac, "=0A= *dsp:=0A= {=0A= do_shilo (SD_, AC, SHIFT6);=0A= }=0A= =0A= 011111,5.RS,00000,000,2.AC,11011,111000:SPECIAL3:32::SHILOV=0A= "shilov ac, r"=0A= *dsp:=0A= {=0A= signed32 shift =3D GPR[RS] & 0x3f;=0A= do_shilo (SD_, AC, shift);=0A= }=0A= =0A= 011111,5.RS,00000,000,2.AC,11111,111000:SPECIAL3:32::MTHLIP=0A= "mthlip r, ac"=0A= *dsp:=0A= {=0A= unsigned32 pos =3D (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;=0A= DSPHI(AC) =3D DSPLO(AC);=0A= DSPLO(AC) =3D GPR[RS];=0A= if (pos >=3D 32)=0A= Unpredictable ();=0A= else=0A= pos +=3D 32;=0A= DSPCR &=3D (~DSPCR_POS_SMASK);=0A= DSPCR |=3D (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;=0A= }=0A= =0A= 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHIdsp=0A= "mfhi r":AC =3D=3D 0=0A= "mfhi r, ac"=0A= *mips32:=0A= *mips32r2:=0A= *mips64:=0A= *mips64r2:=0A= *dsp:=0A= {=0A= if (AC =3D=3D 0)=0A= do_mfhi (SD_, RD);=0A= else=0A= GPR[RD] =3D DSPHI(AC);=0A= }=0A= =0A= 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLOdsp=0A= "mflo r":AC =3D=3D 0=0A= "mflo r, ac"=0A= *mips32:=0A= *mips32r2:=0A= *mips64:=0A= *mips64r2:=0A= *dsp:=0A= {=0A= if (AC =3D=3D 0)=0A= do_mflo (SD_, RD);=0A= else=0A= GPR[RD] =3D DSPLO(AC);=0A= }=0A= =0A= 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHIdsp=0A= "mthi r":AC =3D=3D 0=0A= "mthi r, ac"=0A= *mips32:=0A= *mips32r2:=0A= *mips64:=0A= *mips64r2:=0A= *dsp:=0A= {=0A= if (AC =3D=3D 0)=0A= check_mt_hilo (SD_, HIHISTORY);=0A= DSPHI(AC) =3D GPR[RS];=0A= }=0A= =0A= 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLOdsp=0A= "mtlo r":AC =3D=3D 0=0A= "mtlo r, ac"=0A= *mips32:=0A= *mips32r2:=0A= *mips64:=0A= *mips64r2:=0A= *dsp:=0A= {=0A= if (AC =3D=3D 0)=0A= check_mt_hilo (SD_, LOHISTORY);=0A= DSPLO(AC) =3D GPR[RS];=0A= }=0A= =0A= 011111,5.RS,10.MASK10,10011,111000:SPECIAL3:32::WRDSP=0A= "wrdsp r":MASK10 =3D=3D 1111111111=0A= "wrdsp r, "=0A= *dsp:=0A= {=0A= unsigned32 v1 =3D GPR[RS];=0A= if (MASK10 & 0x1)=0A= {=0A= DSPCR &=3D (~DSPCR_POS_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_POS_SMASK);=0A= }=0A= if (MASK10 & 0x2)=0A= {=0A= DSPCR &=3D (~DSPCR_SCOUNT_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_SCOUNT_SMASK);=0A= }=0A= if (MASK10 & 0x4)=0A= {=0A= DSPCR &=3D (~DSPCR_CARRY_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_CARRY_SMASK);=0A= }=0A= if (MASK10 & 0x8)=0A= {=0A= DSPCR &=3D (~DSPCR_OUFLAG_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_OUFLAG_SMASK);=0A= }=0A= if (MASK10 & 0x10)=0A= {=0A= DSPCR &=3D (~DSPCR_CCOND_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_CCOND_SMASK);=0A= }=0A= if (MASK10 & 0x20)=0A= {=0A= DSPCR &=3D (~DSPCR_EFI_SMASK);=0A= DSPCR |=3D (v1 & DSPCR_EFI_SMASK);=0A= }=0A= }=0A= =0A= 011111,10.MASK10,5.RD,10010,111000:SPECIAL3:32::RDDSP=0A= "rddsp r":MASK10 =3D=3D 1111111111=0A= "rddsp r, "=0A= *dsp:=0A= {=0A= unsigned32 result =3D 0;=0A= if (MASK10 & 0x1)=0A= {=0A= result &=3D (~DSPCR_POS_SMASK);=0A= result |=3D (DSPCR & DSPCR_POS_SMASK);=0A= }=0A= if (MASK10 & 0x2)=0A= {=0A= result &=3D (~DSPCR_SCOUNT_SMASK);=0A= result |=3D (DSPCR & DSPCR_SCOUNT_SMASK);=0A= }=0A= if (MASK10 & 0x4)=0A= {=0A= result &=3D (~DSPCR_CARRY_SMASK);=0A= result |=3D (DSPCR & DSPCR_CARRY_SMASK);=0A= }=0A= if (MASK10 & 0x8)=0A= {=0A= result &=3D (~DSPCR_OUFLAG_SMASK);=0A= result |=3D (DSPCR & DSPCR_OUFLAG_SMASK);=0A= }=0A= if (MASK10 & 0x10)=0A= {=0A= result &=3D (~DSPCR_CCOND_SMASK);=0A= result |=3D (DSPCR & DSPCR_CCOND_SMASK);=0A= }=0A= if (MASK10 & 0x20)=0A= {=0A= result &=3D (~DSPCR_EFI_SMASK);=0A= result |=3D (DSPCR & DSPCR_EFI_SMASK);=0A= }=0A= GPR[RD] =3D EXTEND32 (result);=0A= }=0A= =0A= 011111,5.BASE,5.INDEX,5.RD,00110,001010:SPECIAL3:32::LBUX=0A= "lbux r, r(r)"=0A= *dsp:=0A= {=0A= GPR[RD] =3D do_load (SD_, AccessLength_BYTE, GPR[BASE], GPR[INDEX]);=0A= }=0A= =0A= 011111,5.BASE,5.INDEX,5.RD,00100,001010:SPECIAL3:32::LHX=0A= "lhx r, r(r)"=0A= *dsp:=0A= {=0A= GPR[RD] =3D EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], GPR= [INDEX]));=0A= }=0A= =0A= 011111,5.BASE,5.INDEX,5.RD,00000,001010:SPECIAL3:32::LWX=0A= "lwx r, r(r)"=0A= *dsp:=0A= {=0A= GPR[RD] =3D EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[IND= EX]));=0A= }=0A= =0A= 000001,00000,11100,16.OFFSET:REGIMM:32::BPOSGE32=0A= "bposge32 "=0A= *dsp:=0A= {=0A= unsigned32 pos =3D (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;=0A= address_word offset =3D EXTEND16 (OFFSET) << 2;=0A= if (pos >=3D 32)=0A= {=0A= DELAY_SLOT (NIA + offset);=0A= }=0A= }=0A= ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: application/octet-stream; name="dsp.c" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="dsp.c" Content-length: 1201 /* Simulation code for the MIPS DSP ASE.=0A= Copyright (C) 2005 Free Software Foundation, Inc.=0A= Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.=0A= =0A= This file is part of GDB, the GNU debugger.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */=0A= =0A= #include "sim-main.h"=0A= =0A= int DSPLO_REGNUM[4] =3D=0A= {=0A= AC0LOIDX,=0A= AC1LOIDX,=0A= AC2LOIDX,=0A= AC3LOIDX,=0A= };=0A= =0A= int DSPHI_REGNUM[4] =3D=0A= {=0A= AC0HIIDX,=0A= AC1HIIDX,=0A= AC2HIIDX,=0A= AC3HIIDX,=0A= };=0A= ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: application/octet-stream; name="mips32-dsp.s" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="mips32-dsp.s" Content-length: 38702 # MIPS32 DSP ASE test=0A= # mach: mips32 mips64=0A= #as: -mdsp=0A= #ld: -N -Ttext=3D0x80010000=0A= #output: *\\npass\\n=0A= =0A= # Copyright (C) 2005 Free Software Foundation, Inc.=0A= # Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.=0A= #=0A= # This file is part of the GNU simulators.=0A= #=0A= # This program is free software; you can redistribute it and/or modify=0A= # it under the terms of the GNU General Public License as published by=0A= # the Free Software Foundation; either version 2, or (at your option)=0A= # any later version.=0A= #=0A= # This program is distributed in the hope that it will be useful,=0A= # but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= # GNU General Public License for more details.=0A= #=0A= # You should have received a copy of the GNU General Public License along= =0A= # with this program; if not, write to the Free Software Foundation, Inc.,= =0A= # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */=0A= =0A= .include "testutils.inc"=0A= .include "utils-dsp.inc"=0A= =0A= setup=0A= =0A= .set noreorder=0A= =0A= .ent DIAG=0A= DIAG:=0A= =0A= writemsg "[1] Test addq.ph"=0A= dspck_dstio addq.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addq.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0=0A= dspck_dstio addq.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0=0A= dspck_dstio addq.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0=0A= dspck_dstio addq.ph, 0x0, 0xffffffff, 0x10001, 0x0, 0x0=0A= =0A= writemsg "[2] Test addq_s.ph"=0A= dspck_dstio addq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addq_s.ph, 0x20002, 0x10001, 0x10001, 0x0, 0x0=0A= dspck_dstio addq_s.ph, 0xfffefffe, 0xffffffff, 0xffffffff, 0x0, 0x0=0A= dspck_dstio addq_s.ph, 0xffff0000, 0xffffffff, 0x1, 0x0, 0x0=0A= dspck_dstio addq_s.ph, 0xffff0000, 0x1, 0xffffffff, 0x0, 0x0=0A= =0A= writemsg "[3] Test addq_s.w"=0A= dspck_dsti addq_s.w, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addq_s.w, 0x2, 0x1, 0x1, 0x0, 0x0=0A= dspck_dstio addq_s.w, 0xfffffffe, 0xffffffff, 0xffffffff, 0x0, 0x0=0A= dspck_dstio addq_s.w, 0x0, 0xffffffff, 0x1, 0x0, 0x0=0A= dspck_dstio addq_s.w, 0xffff, 0xffffffff, 0x10000, 0x0, 0x0=0A= =0A= writemsg "[4] Test addu.qb"=0A= dspck_dstio addu.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addu.qb, 0x2040000, 0x102ff01, 0x10201ff, 0x0, 0x100000=0A= dspck_dstio addu.qb, 0xfe0001fe, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000=0A= dspck_dstio addu.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0=0A= dspck_dstio addu.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0=0A= =0A= writemsg "[5] Test addu_s.qb"=0A= dspck_dstio addu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addu_s.qb, 0x204ffff, 0x102ff01, 0x10201ff, 0x0, 0x100000=0A= dspck_dstio addu_s.qb, 0xfeffffff, 0x7f80ffff, 0x7f8002ff, 0x0, 0x100000= =0A= dspck_dstio addu_s.qb, 0xffffffff, 0x10203, 0xfffefdfc, 0x0, 0x0=0A= dspck_dstio addu_s.qb, 0xffffffff, 0xfbfaf9f8, 0x4050607, 0x0, 0x0=0A= =0A= writemsg "[6] Test subq.ph"=0A= dspck_dstio subq.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio subq.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0=0A= dspck_dstio subq.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0=0A= dspck_dstio subq.ph, 0x7fff0000, 0xfffe8000, 0x7fff8000, 0x0, 0x100000=0A= dspck_dstio subq.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0=0A= =0A= writemsg "[7] Test subq_s.ph"=0A= dspck_dstio subq_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio subq_s.ph, 0x10001, 0x20002, 0x10001, 0x0, 0x0=0A= dspck_dstio subq_s.ph, 0x1ffff, 0x2fffe, 0x1ffff, 0x0, 0x0=0A= dspck_dstio subq_s.ph, 0x0, 0x7fff8000, 0x7fff8000, 0x0, 0x0=0A= dspck_dstio subq_s.ph, 0x1ffff, 0x7fff8000, 0x7ffe8001, 0x0, 0x0=0A= =0A= writemsg "[8] Test subq_s.w"=0A= dspck_dsti subq_s.w, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsti subq_s.w, 0x0, 0x7fffffff, 0x7fffffff, 0x0=0A= dspck_dstio subq_s.w, 0x7fffffff, 0x0, 0x80000000, 0x0, 0x100000=0A= dspck_dstio subq_s.w, 0x1, 0x2, 0x1, 0x0, 0x0=0A= dspck_dstio subq_s.w, 0xffffffff, 0xfffffffe, 0xffffffff, 0x0, 0x0=0A= =0A= writemsg "[9] Test subu.qb"=0A= dspck_dstio subu.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio subu.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0=0A= dspck_dstio subu.qb, 0xfcfdfeff, 0x4030201, 0x8060402, 0x0, 0x100000=0A= dspck_dstio subu.qb, 0x102ff01, 0x2040000, 0x10201ff, 0x0, 0x100000=0A= dspck_dstio subu.qb, 0x7f80ffff, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000=0A= =0A= writemsg "[10] Test subu_s.qb"=0A= dspck_dstio subu_s.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio subu_s.qb, 0x4030201, 0x8060402, 0x4030201, 0x0, 0x0=0A= dspck_dstio subu_s.qb, 0x0, 0x4030201, 0x8060402, 0x0, 0x100000=0A= dspck_dstio subu_s.qb, 0x1020000, 0x2040000, 0x10201ff, 0x0, 0x100000=0A= dspck_dstio subu_s.qb, 0x7f000000, 0xfe0001fe, 0x7f8002ff, 0x0, 0x100000= =0A= =0A= writemsg "[11] Test addsc"=0A= dspck_dstio addsc, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addsc, 0x1000000, 0x84000000, 0x7d000000, 0x0, 0x2000=0A= dspck_dstio addsc, 0xf1000000, 0x74000000, 0x7d000000, 0x0, 0x0=0A= dspck_dstio addsc, 0x2, 0x1, 0x1, 0x0, 0x0=0A= dspck_dstio addsc, 0xffffffff, 0xfffffffe, 0x1, 0x0, 0x0=0A= =0A= writemsg "[12] Test addwc"=0A= dspck_dstio addwc, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio addwc, 0x2, 0x1, 0x1, 0x0, 0x0=0A= dspck_dstio addwc, 0x3, 0x1, 0x1, 0x2000, 0x2000=0A= dspck_dsti addwc, 0x1, 0xffffffff, 0x1, 0x2000=0A= dspck_dsti addwc, 0x11, 0xa, 0x6, 0x2000=0A= =0A= writemsg "[13] Test modsub"=0A= dspck_dstio modsub, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio modsub, 0x76, 0x78, 0x7802, 0x0, 0x0=0A= dspck_dstio modsub, 0x74, 0x76, 0x7802, 0x0, 0x0=0A= dspck_dstio modsub, 0x78, 0x0, 0x7802, 0x0, 0x0=0A= dspck_dstio modsub, 0xf9, 0xfc, 0xfe03, 0x0, 0x0=0A= =0A= writemsg "[14] Test raddu.w.qb"=0A= dspck_dsio raddu.w.qb, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio raddu.w.qb, 0x2, 0x1000100, 0x0, 0x0=0A= dspck_dsio raddu.w.qb, 0x4, 0x1010101, 0x0, 0x0=0A= dspck_dsio raddu.w.qb, 0x200, 0xff01ff01, 0x0, 0x0=0A= dspck_dsio raddu.w.qb, 0x3fc, 0xffffffff, 0x0, 0x0=0A= =0A= writemsg "[15] Test absq_s.ph"=0A= dspck_dsio absq_s.ph, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio absq_s.ph, 0x10001, 0xffffffff, 0x0, 0x0=0A= dspck_dsio absq_s.ph, 0x7fff7fff, 0x80008000, 0x0, 0x100000=0A= dspck_dsio absq_s.ph, 0x60000002, 0xa000fffe, 0x0, 0x0=0A= dspck_dsio absq_s.ph, 0x70000004, 0x9000fffc, 0x0, 0x0=0A= =0A= writemsg "[16] Test absq_s.w"=0A= dspck_dsio absq_s.w, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio absq_s.w, 0x1, 0xffffffff, 0x0, 0x0=0A= dspck_dsio absq_s.w, 0x7fffffff, 0x80000000, 0x0, 0x100000=0A= dspck_dsio absq_s.w, 0x40000001, 0xbfffffff, 0x0, 0x0=0A= dspck_dsio absq_s.w, 0x8000001, 0xf7ffffff, 0x0, 0x0=0A= =0A= writemsg "[17] Test precrq.qb.ph"=0A= dspck_dstio precrq.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio precrq.qb.ph, 0xff7f4020, 0xffff7fff, 0x40002000, 0x0, 0x0=0A= dspck_dstio precrq.qb.ph, 0xfeba7632, 0xfedcba98, 0x76543210, 0x0, 0x0=0A= dspck_dstio precrq.qb.ph, 0x7632feba, 0x76543210, 0xfedcba98, 0x0, 0x0=0A= dspck_dstio precrq.qb.ph, 0x14589cd, 0x1234567, 0x89abcdef, 0x0, 0x0=0A= =0A= writemsg "[18] Test precrq.ph.w"=0A= dspck_dstio precrq.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio precrq.ph.w, 0xffff4000, 0xffff7fff, 0x40002000, 0x0, 0x0=0A= dspck_dstio precrq.ph.w, 0xfedc7654, 0xfedcba98, 0x76543210, 0x0, 0x0=0A= dspck_dstio precrq.ph.w, 0x7654fedc, 0x76543210, 0xfedcba98, 0x0, 0x0=0A= dspck_dstio precrq.ph.w, 0x12389ab, 0x1234567, 0x89abcdef, 0x0, 0x0=0A= =0A= writemsg "[19] Test precrq_rs.ph.w"=0A= dspck_dstio precrq_rs.ph.w, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio precrq_rs.ph.w, 0x7fff0000, 0x7fffffff, 0xffffffff, 0x0, 0x400= 000=0A= dspck_dstio precrq_rs.ph.w, 0x80008001, 0x80007fff, 0x8000ffff, 0x0, 0x0= =0A= dspck_dstio precrq_rs.ph.w, 0xfedd7654, 0xfedcba98, 0x76543210, 0x0, 0x0= =0A= dspck_dstio precrq_rs.ph.w, 0x7654fedd, 0x76543210, 0xfedcba98, 0x0, 0x0= =0A= =0A= writemsg "[20] Test precrqu_s.qb.ph"=0A= dspck_dstio precrqu_s.qb.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio precrqu_s.qb.ph, 0xff8040, 0xffff7fff, 0x40002000, 0x0, 0x4000= 00=0A= dspck_dstio precrqu_s.qb.ph, 0xec64, 0xfedcba98, 0x76543210, 0x0, 0x400000= =0A= dspck_dstio precrqu_s.qb.ph, 0xec640000, 0x76543210, 0xfedcba98, 0x0, 0x40= 0000=0A= dspck_dstio precrqu_s.qb.ph, 0x28a0000, 0x1234567, 0x89abcdef, 0x0, 0x4000= 00=0A= =0A= writemsg "[21] Test preceq.w.phl"=0A= dspck_dsio preceq.w.phl, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceq.w.phl, 0xffff0000, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceq.w.phl, 0x80000000, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceq.w.phl, 0xc0010000, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceq.w.phl, 0x76540000, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[22] Test preceq.w.phr"=0A= dspck_dsio preceq.w.phr, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceq.w.phr, 0xffff0000, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceq.w.phr, 0x40000000, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceq.w.phr, 0x20010000, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceq.w.phr, 0x32100000, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[23] Test precequ.ph.qbl"=0A= dspck_dsio precequ.ph.qbl, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbl, 0x7f807f80, 0xffffffff, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbl, 0x40000000, 0x80004000, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbl, 0x60000080, 0xc0012001, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbl, 0x3b002a00, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[24] Test precequ.ph.qbr"=0A= dspck_dsio precequ.ph.qbr, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbr, 0x7f807f80, 0xffffffff, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbr, 0x20000000, 0x80004000, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbr, 0x10000080, 0xc0012001, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbr, 0x19000800, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[25] Test precequ.ph.qbla"=0A= dspck_dsio precequ.ph.qbla, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbla, 0x7f807f80, 0xffffffff, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbla, 0x40002000, 0x80004000, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbla, 0x60001000, 0xc0012001, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbla, 0x3b001900, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[26] Test precequ.ph.qbra"=0A= dspck_dsio precequ.ph.qbra, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbra, 0x7f807f80, 0xffffffff, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbra, 0x0, 0x80004000, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbra, 0x800080, 0xc0012001, 0x0, 0x0=0A= dspck_dsio precequ.ph.qbra, 0x2a000800, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[27] Test preceu.ph.qbl"=0A= dspck_dsio preceu.ph.qbl, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbl, 0xff00ff, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbl, 0x800000, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbl, 0xc00001, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbl, 0x760054, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[28] Test preceu.ph.qbr"=0A= dspck_dsio preceu.ph.qbr, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbr, 0xff00ff, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbr, 0x400000, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbr, 0x200001, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbr, 0x320010, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[29] Test preceu.ph.qbla"=0A= dspck_dsio preceu.ph.qbla, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbla, 0xff00ff, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbla, 0x800040, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbla, 0xc00020, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbla, 0x760032, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[30] Test preceu.ph.qbra"=0A= dspck_dsio preceu.ph.qbra, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbra, 0xff00ff, 0xffffffff, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbra, 0x0, 0x80004000, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbra, 0x10001, 0xc0012001, 0x0, 0x0=0A= dspck_dsio preceu.ph.qbra, 0x540010, 0x76543210, 0x0, 0x0=0A= =0A= writemsg "[31] Test shll.qb"=0A= dspck_dtsaio shll.qb, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_dtsai shll.qb, 0x202fefe, 0x101ffff, 1, 0x0=0A= dspck_dtsai shll.qb, 0xfefe0002, 0x7fff8081, 1, 0x0=0A= dspck_dtsai shll.qb, 0xfcfc0020, 0x7fff8008, 2, 0x0=0A= dspck_dtsai shll.qb, 0x68b0d868, 0x6db6db6d, 3, 0x0=0A= =0A= writemsg "[32] Test shllv.qb"=0A= dspck_dstio shllv.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsti shllv.qb, 0x202fefe, 0x101ffff, 0x1, 0x0=0A= dspck_dsti shllv.qb, 0xfefe0002, 0x7fff8081, 0x1, 0x0=0A= dspck_dsti shllv.qb, 0xfcfc0020, 0x7fff8008, 0x2, 0x0=0A= dspck_dsti shllv.qb, 0x68b0d868, 0x6db6db6d, 0x3, 0x0=0A= =0A= writemsg "[33] Test shll.ph"=0A= dspck_dtsaio shll.ph, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_dtsaio shll.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0=0A= dspck_dtsaio shll.ph, 0xfffe0000, 0x7fff8000, 1, 0x0, 0x400000=0A= dspck_dtsaio shll.ph, 0xfffc0020, 0x7fff8008, 2, 0x0, 0x400000=0A= dspck_dtsaio shll.ph, 0x6db0db68, 0x6db6db6d, 3, 0x0, 0x400000=0A= =0A= writemsg "[34] Test shllv.ph"=0A= dspck_dstio shllv.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio shllv.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0=0A= dspck_dstio shllv.ph, 0xfffe0000, 0x7fff8000, 0x1, 0x0, 0x400000=0A= dspck_dstio shllv.ph, 0xfffc0020, 0x7fff8008, 0x2, 0x0, 0x400000=0A= dspck_dstio shllv.ph, 0x6db0db68, 0x6db6db6d, 0x3, 0x0, 0x400000=0A= =0A= writemsg "[35] Test shll_s.ph"=0A= dspck_dtsaio shll_s.ph, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_dtsaio shll_s.ph, 0x2fffe, 0x1ffff, 1, 0x0, 0x0=0A= dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8000, 1, 0x0, 0x400000=0A= dspck_dtsaio shll_s.ph, 0x7fff8000, 0x7fff8008, 2, 0x0, 0x400000=0A= dspck_dtsaio shll_s.ph, 0x7fff8000, 0x6db6db6d, 3, 0x0, 0x400000=0A= =0A= writemsg "[36] Test shllv_s.ph"=0A= dspck_dstio shllv_s.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio shllv_s.ph, 0x2fffe, 0x1ffff, 0x1, 0x0, 0x0=0A= dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8000, 0x1, 0x0, 0x400000=0A= dspck_dstio shllv_s.ph, 0x7fff8000, 0x7fff8008, 0x2, 0x0, 0x400000=0A= dspck_dstio shllv_s.ph, 0x7fff8000, 0x6db6db6d, 0x3, 0x0, 0x400000=0A= =0A= writemsg "[37] Test shll_s.w"=0A= dspck_dtsaio shll_s.w, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_dtsaio shll_s.w, 0x3fffe, 0x1ffff, 1, 0x0, 0x0=0A= dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8000, 1, 0x0, 0x400000=0A= dspck_dtsaio shll_s.w, 0x80000000, 0x80000000, 1, 0x0, 0x400000=0A= dspck_dtsaio shll_s.w, 0x7fffffff, 0x7fff8008, 2, 0x0, 0x400000=0A= =0A= writemsg "[38] Test shllv_s.w"=0A= dspck_dstio shllv_s.w, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio shllv_s.w, 0x3fffe, 0x1ffff, 0x1, 0x0, 0x0=0A= dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8000, 0x1, 0x0, 0x400000=0A= dspck_dstio shllv_s.w, 0x80000000, 0x80000000, 0x1, 0x0, 0x400000=0A= dspck_dstio shllv_s.w, 0x7fffffff, 0x7fff8008, 0x2, 0x0, 0x400000=0A= =0A= writemsg "[39] Test shrl.qb"=0A= dspck_dtsaio shrl.qb, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_dtsai shrl.qb, 0x7f7f, 0x101ffff, 1, 0x0=0A= dspck_dtsai shrl.qb, 0x3f7f4040, 0x7fff8081, 1, 0x0=0A= dspck_dtsai shrl.qb, 0x1f3f2002, 0x7fff8008, 2, 0x0=0A= dspck_dtsai shrl.qb, 0xd161b0d, 0x6db6db6d, 3, 0x0=0A= =0A= writemsg "[40] Test shrlv.qb"=0A= dspck_dstio shrlv.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsti shrlv.qb, 0x7f7f, 0x101ffff, 0x1, 0x0=0A= dspck_dsti shrlv.qb, 0x3f7f4040, 0x7fff8081, 0x1, 0x0=0A= dspck_dsti shrlv.qb, 0x1f3f2002, 0x7fff8008, 0x2, 0x0=0A= dspck_dsti shrlv.qb, 0xd161b0d, 0x6db6db6d, 0x3, 0x0=0A= =0A= writemsg "[41] Test shra.ph"=0A= dspck_dtsaio shra.ph, 0x10001, 0x20002, 1, 0x0, 0x0=0A= dspck_dtsaio shra.ph, 0x10006, 0x10106f6f, 12, 0x0, 0x0=0A= dspck_dtsaio shra.ph, 0x1c000, 0x28000, 1, 0x0, 0x0=0A= dspck_dtsaio shra.ph, 0x2f800, 0x208000, 4, 0x0, 0x0=0A= dspck_dtsaio shra.ph, 0xfc01fc00, 0x80208000, 5, 0x0, 0x0=0A= =0A= writemsg "[42] Test shrav.ph"=0A= dspck_dstio shrav.ph, 0x10001, 0x20002, 0x1, 0x0, 0x0=0A= dspck_dstio shrav.ph, 0x10006, 0x10106f6f, 0xc, 0x0, 0x0=0A= dspck_dstio shrav.ph, 0x1c000, 0x28000, 0x1, 0x0, 0x0=0A= dspck_dstio shrav.ph, 0x2f800, 0x208000, 0x4, 0x0, 0x0=0A= dspck_dstio shrav.ph, 0xfc01fc00, 0x80208000, 0x5, 0x0, 0x0=0A= =0A= writemsg "[43] Test shra_r.ph"=0A= dspck_dtsaio shra_r.ph, 0x20001, 0x30002, 1, 0x0, 0x0=0A= dspck_dtsaio shra_r.ph, 0x10001, 0x20001, 1, 0x0, 0x0=0A= dspck_dtsaio shra_r.ph, 0x10001, 0x10001, 1, 0x0, 0x0=0A= dspck_dtsaio shra_r.ph, 0x0, 0x10001, 2, 0x0, 0x0=0A= =0A= writemsg "[44] Test shrav_r.ph"=0A= dspck_dstio shrav_r.ph, 0x20001, 0x30002, 0x1, 0x0, 0x0=0A= dspck_dstio shrav_r.ph, 0x10001, 0x20001, 0x1, 0x0, 0x0=0A= dspck_dstio shrav_r.ph, 0x10001, 0x10001, 0x1, 0x0, 0x0=0A= dspck_dstio shrav_r.ph, 0x0, 0x10001, 0x2, 0x0, 0x0=0A= =0A= writemsg "[45] Test shra_r.w"=0A= dspck_dtsaio shra_r.w, 0x1, 0x2, 1, 0x0, 0x0=0A= dspck_dtsaio shra_r.w, 0xffff8000, 0x80000000, 16, 0x0, 0x0=0A= dspck_dtsaio shra_r.w, 0x8001, 0x10001, 1, 0x0, 0x0=0A= dspck_dtsaio shra_r.w, 0x1, 0x10001, 17, 0x0, 0x0=0A= dspck_dtsaio shra_r.w, 0xffffc001, 0x80010001, 17, 0x0, 0x0=0A= =0A= writemsg "[46] Test shrav_r.w"=0A= dspck_dstio shrav_r.w, 0x1, 0x2, 0x1, 0x0, 0x0=0A= dspck_dstio shrav_r.w, 0xffff8000, 0x80000000, 0x10, 0x0, 0x0=0A= dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x1, 0x0, 0x0=0A= dspck_dstio shrav_r.w, 0x8001, 0x10001, 0x21, 0x0, 0x0=0A= dspck_dstio shrav_r.w, 0x4000, 0x10001, 0x2, 0x0, 0x0=0A= =0A= writemsg "[47] Test muleu_s.ph.qbl"=0A= dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbl, 0x0, 0x0, 0x40004000, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbl, 0x0, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbl, 0x10001, 0x1010101, 0x10001, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbl, 0x10000, 0x1000001, 0x10001, 0x0, 0x0=0A= =0A= writemsg "[48] Test muleu_s.ph.qbr"=0A= dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbr, 0x0, 0x0, 0x40004000, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbr, 0x0, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbr, 0x10001, 0x1010101, 0x10001, 0x0, 0x0=0A= dspck_dstio muleu_s.ph.qbr, 0x1, 0x1000001, 0x10001, 0x0, 0x0=0A= =0A= writemsg "[49] Test mulq_rs.ph"=0A= dspck_dstio mulq_rs.ph, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio mulq_rs.ph, 0x0, 0x1, 0x1, 0x0, 0x0=0A= dspck_dstio mulq_rs.ph, 0x20000000, 0x40007fff, 0x40000000, 0x0, 0x0=0A= dspck_dstio mulq_rs.ph, 0x33330000, 0x66660000, 0x40007fff, 0x0, 0x0=0A= dspck_dstio mulq_rs.ph, 0xccd3332, 0x66666666, 0x10003fff, 0x0, 0x0=0A= =0A= writemsg "[50] Test muleq_s.w.phl"=0A= dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0x40004000, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phl, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phl, 0x0, 0x0, 0xc000c000, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phl, 0x0, 0x80008000, 0x0, 0x0, 0x0=0A= =0A= writemsg "[51] Test muleq_s.w.phr"=0A= dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0x40004000, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phr, 0x0, 0x7fff7fff, 0x0, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phr, 0x0, 0x0, 0xc000c000, 0x0, 0x0=0A= dspck_dstio muleq_s.w.phr, 0x0, 0x80008000, 0x0, 0x0, 0x0=0A= =0A= writemsg "[52] Test dpau.h.qbl"=0A= dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0= =0A= dspck_astio dpau.h.qbl, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x100= 0001, 0x0, 0x0=0A= dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0= =0A= dspck_astio dpau.h.qbl, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0= =0A= =0A= writemsg "[53] Test dpau.h.qbr"=0A= dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x1, 0x1010101, 0x1000001, 0x0, 0x0= =0A= dspck_astio dpau.h.qbr, 0xffffffff, 0xffffffff, 0x0, 0x0, 0x1010101, 0x100= 0001, 0x0, 0x0=0A= dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0= =0A= dspck_astio dpau.h.qbr, 0x0, 0x0, 0x0, 0xff, 0xffff0001, 0x1ffff, 0x0, 0x0= =0A= =0A= writemsg "[54] Test dpsu.h.qbl"=0A= dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpsu.h.qbl, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0= =0A= dspck_astio dpsu.h.qbl, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x100= 0001, 0x0, 0x0=0A= dspck_astio dpsu.h.qbl, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0= =0A= dspck_astio dpsu.h.qbl, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0= =0A= =0A= writemsg "[55] Test dpsu.h.qbr"=0A= dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpsu.h.qbr, 0x0, 0x1, 0x0, 0x0, 0x1010101, 0x1000001, 0x0, 0x0= =0A= dspck_astio dpsu.h.qbr, 0x0, 0x0, 0xffffffff, 0xffffffff, 0x1010101, 0x100= 0001, 0x0, 0x0=0A= dspck_astio dpsu.h.qbr, 0x0, 0x0, 0x0, 0x0, 0xffff0000, 0xffff, 0x0, 0x0= =0A= dspck_astio dpsu.h.qbr, 0x0, 0xff, 0x0, 0x0, 0xffff0001, 0x1ffff, 0x0, 0x0= =0A= =0A= writemsg "[56] Test dpaq_s.w.ph"=0A= dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffc0004, 0x7fff7fff, 0x7fff7fff= , 0x0, 0x0=0A= dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0x0, 0xfffffffe, 0x80008000, 0x80008000= , 0x0, 0xf0000=0A= dspck_astio dpaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0xa0000000, 0x40002000, 0x8= 0008000, 0x0, 0x0=0A= dspck_astio dpaq_s.w.ph, 0xffffffff, 0xa0000000, 0xffffffff, 0x88000000, 0= x10000800, 0x80008000, 0x0, 0x0=0A= =0A= writemsg "[57] Test dpsq_s.w.ph"=0A= dspck_astio dpsq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpsq_s.w.ph, 0x0, 0xfffc0004, 0x0, 0x0, 0x7fff7fff, 0x7fff7fff= , 0x0, 0x0=0A= dspck_astio dpsq_s.w.ph, 0x0, 0xfffffffe, 0x0, 0x0, 0x80008000, 0x80008000= , 0x0, 0xf0000=0A= dspck_astio dpsq_s.w.ph, 0xffffffff, 0xa0000000, 0x0, 0x0, 0x40002000, 0x8= 0008000, 0x0, 0x0=0A= dspck_astio dpsq_s.w.ph, 0xffffffff, 0x88000000, 0xffffffff, 0xa0000000, 0= x10000800, 0x80008000, 0x0, 0x0=0A= =0A= writemsg "[58] Test mulsaq_s.w.ph"=0A= dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x0, 0x4000, 0xc0000000, 0x0, 0x= 0=0A= dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0xffffffff, 0x60010000, 0x80004000, 0= x7fff4000, 0x0, 0x0=0A= dspck_astio mulsaq_s.w.ph, 0x0, 0x0, 0x0, 0x5fffffff, 0x80004000, 0x800040= 00, 0x0, 0xf0000=0A= dspck_astio mulsaq_s.w.ph, 0x7fffffff, 0xffffffff, 0x80000000, 0xfffc0003,= 0x7fff8001, 0x7fff7fff, 0x0, 0x0=0A= =0A= writemsg "[59] Test dpaq_sa.l.w"=0A= dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7ffffffe, 0x2, 0x7fffffff, 0x7fffffff= , 0x0, 0x0=0A= dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0x7fffffff, 0xffffffff, 0x80000000, 0x8= 0000000, 0x0, 0xf0000=0A= dspck_astio dpaq_sa.l.w, 0x0, 0x0, 0xc0000000, 0x80000000, 0xc0000000, 0x7= fffffff, 0x0, 0x0=0A= dspck_astio dpaq_sa.l.w, 0x20000000, 0x0, 0x0, 0x40000000, 0xe0000000, 0x7= fffffff, 0x0, 0x0=0A= =0A= writemsg "[60] Test dpsq_sa.l.w"=0A= dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio dpsq_sa.l.w, 0x7fffffff, 0xffffffff, 0x0, 0x0, 0x80000000, 0x8= 0000000, 0x0, 0xf0000=0A= dspck_astio dpsq_sa.l.w, 0x80000000, 0x0, 0x80000000, 0x0, 0x80000000, 0x8= 0000000, 0x0, 0xf0000=0A= dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x80000000, 0x1, 0x80000000, 0x80000000= , 0x0, 0xf0000=0A= dspck_astio dpsq_sa.l.w, 0x0, 0x0, 0x3fffffff, 0x80000000, 0xc0000000, 0x7= fffffff, 0x0, 0x0=0A= =0A= writemsg "[61] Test maq_s.w.phl"=0A= dspck_astio maq_s.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000= , 0x0, 0x0=0A= dspck_astio maq_s.w.phl, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0= , 0x0, 0x0=0A= dspck_astio maq_s.w.phl, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0= , 0x0, 0x0=0A= dspck_astio maq_s.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000= , 0x0, 0x0=0A= =0A= writemsg "[62] Test maq_s.w.phr"=0A= dspck_astio maq_s.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x0, 0x40004000= , 0x0, 0x0=0A= dspck_astio maq_s.w.phr, 0x0, 0xffffffff, 0x0, 0xffffffff, 0x7fff7fff, 0x0= , 0x0, 0x0=0A= dspck_astio maq_s.w.phr, 0xffffffff, 0x0, 0xffffffff, 0x0, 0x7fff7fff, 0x0= , 0x0, 0x0=0A= dspck_astio maq_s.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c000= , 0x0, 0x0=0A= =0A= writemsg "[63] Test maq_sa.w.phl"=0A= dspck_astio maq_sa.w.phl, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, = 0x0, 0x40004000, 0x0, 0x0=0A= dspck_astio maq_sa.w.phl, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x= 0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phl, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, = 0x7fff7fff, 0x0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phl, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c00= 0, 0x0, 0x0=0A= =0A= writemsg "[64] Test maq_sa.w.phr"=0A= dspck_astio maq_sa.w.phr, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, = 0x0, 0x40004000, 0x0, 0x0=0A= dspck_astio maq_sa.w.phr, 0x0, 0x7fffffff, 0x0, 0x7fffffff, 0x7fff7fff, 0x= 0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phr, 0xffffffff, 0x80000000, 0xffffffff, 0x80000000, = 0x7fff7fff, 0x0, 0x0, 0x0=0A= dspck_astio maq_sa.w.phr, 0x0, 0x40000000, 0x0, 0x40000000, 0x0, 0xc000c00= 0, 0x0, 0x0=0A= =0A= writemsg "[65] Test bitrev"=0A= dspck_dsio bitrev, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio bitrev, 0x1, 0x8000, 0x0, 0x0=0A= dspck_dsio bitrev, 0x8000, 0x1, 0x0, 0x0=0A= dspck_dsio bitrev, 0xc0c0, 0x1010303, 0x0, 0x0=0A= dspck_dsio bitrev, 0x1, 0xffff8000, 0x0, 0x0=0A= =0A= writemsg "[66] Test insv"=0A= dspck_tsi insv, 0xf0caf0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x311=0A= dspck_tsi insv, 0x7fffffe, 0x0, 0x7ffffff, 0xd01=0A= dspck_tsi insv, 0x3fff, 0x0, 0x3fff, 0x700=0A= dspck_tsi insv, 0xf0f2f0f0, 0xf0f0f0f0, 0xa5a5a5a5, 0x28f=0A= dspck_tsi insv, 0x3fc, 0x0, 0x3ff, 0x402=0A= =0A= writemsg "[67] Test repl.qb"=0A= dspck_dIio repl.qb, 0x0, 0, 0x0, 0x0=0A= dspck_dIio repl.qb, 0x1010101, 1, 0x0, 0x0=0A= dspck_dIio repl.qb, 0xffffffff, 255, 0x0, 0x0=0A= dspck_dIio repl.qb, 0x7f7f7f7f, 127, 0x0, 0x0=0A= dspck_dIio repl.qb, 0xfefefefe, 254, 0x0, 0x0=0A= =0A= writemsg "[68] Test replv.qb"=0A= dspck_dsio replv.qb, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio replv.qb, 0x1010101, 0x1, 0x0, 0x0=0A= dspck_dsio replv.qb, 0xffffffff, 0xff, 0x0, 0x0=0A= dspck_dsio replv.qb, 0x7f7f7f7f, 0x37f, 0x0, 0x0=0A= dspck_dsio replv.qb, 0xfefefefe, 0xfffffffe, 0x0, 0x0=0A= =0A= writemsg "[69] Test repl.ph"=0A= dspck_dIio repl.ph, 0x0, 0, 0x0, 0x0=0A= dspck_dIio repl.ph, 0x10001, 1, 0x0, 0x0=0A= dspck_dIio repl.ph, 0xffffffff, -1, 0x0, 0x0=0A= dspck_dIio repl.ph, 0xff7fff7f, -129, 0x0, 0x0=0A= dspck_dIio repl.ph, 0xfffefffe, -2, 0x0, 0x0=0A= =0A= writemsg "[70] Test replv.ph"=0A= dspck_dsio replv.ph, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsio replv.ph, 0x10001, 0x1, 0x0, 0x0=0A= dspck_dsio replv.ph, 0xffffffff, 0x5555ffff, 0x0, 0x0=0A= dspck_dsio replv.ph, 0x37f037f, 0x37f, 0x0, 0x0=0A= dspck_dsio replv.ph, 0xfffefffe, 0xfffffffe, 0x0, 0x0=0A= =0A= writemsg "[71] Test cmpu.eq.qb"=0A= dspck_stio cmpu.eq.qb, 0x0, 0x0, 0x0, 0xf000000=0A= dspck_stio cmpu.eq.qb, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_stio cmpu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmpu.eq.qb, 0x10203, 0x4050607, 0x0, 0x0=0A= dspck_stio cmpu.eq.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0=0A= =0A= writemsg "[72] Test cmpu.lt.qb"=0A= dspck_stio cmpu.lt.qb, 0x0, 0x0, 0x0, 0x0=0A= dspck_stio cmpu.lt.qb, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_stio cmpu.lt.qb, 0x0, 0xffffffff, 0x0, 0xf000000=0A= dspck_stio cmpu.lt.qb, 0x10203, 0x4050607, 0x0, 0xf000000=0A= dspck_stio cmpu.lt.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000=0A= =0A= writemsg "[73] Test cmpu.le.qb"=0A= dspck_stio cmpu.le.qb, 0x0, 0x0, 0x0, 0xf000000=0A= dspck_stio cmpu.le.qb, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_stio cmpu.le.qb, 0x0, 0xffffffff, 0x0, 0xf000000=0A= dspck_stio cmpu.le.qb, 0x10203, 0x4050607, 0x0, 0xf000000=0A= dspck_stio cmpu.le.qb, 0x8090a0b, 0xc0d0e0f, 0x0, 0xf000000=0A= =0A= writemsg "[74] Test cmpgu.eq.qb"=0A= dspck_dstio cmpgu.eq.qb, 0xf, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.eq.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.eq.qb, 0x0, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_dstio cmpgu.eq.qb, 0x0, 0x10203, 0x4050607, 0x0, 0x0=0A= dspck_dstio cmpgu.eq.qb, 0x0, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0=0A= =0A= writemsg "[75] Test cmpgu.lt.qb"=0A= dspck_dstio cmpgu.lt.qb, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.lt.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.lt.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_dstio cmpgu.lt.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0=0A= dspck_dstio cmpgu.lt.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0=0A= =0A= writemsg "[76] Test cmpgu.le.qb"=0A= dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.le.qb, 0x0, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_dstio cmpgu.le.qb, 0xf, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_dstio cmpgu.le.qb, 0xf, 0x10203, 0x4050607, 0x0, 0x0=0A= dspck_dstio cmpgu.le.qb, 0xf, 0x8090a0b, 0xc0d0e0f, 0x0, 0x0=0A= =0A= writemsg "[77] Test cmp.eq.ph"=0A= dspck_stio cmp.eq.ph, 0x0, 0x0, 0x0, 0x3000000=0A= dspck_stio cmp.eq.ph, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.eq.ph, 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_stio cmp.eq.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.eq.ph, 0x11112222, 0x33334444, 0x0, 0x0=0A= =0A= writemsg "[78] Test cmp.lt.ph"=0A= dspck_stio cmp.lt.ph, 0x0, 0x0, 0x0, 0x0=0A= dspck_stio cmp.lt.ph, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.lt.ph, 0xffffffff, 0x0, 0x0, 0x3000000=0A= dspck_stio cmp.lt.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.lt.ph, 0x11112222, 0x33334444, 0x0, 0x3000000=0A= =0A= writemsg "[79] Test cmp.le.ph"=0A= dspck_stio cmp.le.ph, 0x0, 0x0, 0x0, 0x3000000=0A= dspck_stio cmp.le.ph, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.le.ph, 0xffffffff, 0x0, 0x0, 0x3000000=0A= dspck_stio cmp.le.ph, 0x7fff7fff, 0xffffffff, 0x0, 0x0=0A= dspck_stio cmp.le.ph, 0x11112222, 0x33334444, 0x0, 0x3000000=0A= =0A= writemsg "[80] Test pick.qb"=0A= dspck_dsti pick.qb, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsti pick.qb, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_dsti pick.qb, 0xffffffff, 0xffffffff, 0x0, 0xf000000=0A= dspck_dsti pick.qb, 0xff, 0xffffffff, 0x0, 0x1000000=0A= dspck_dsti pick.qb, 0xff00, 0xffffffff, 0x0, 0x2000000=0A= =0A= writemsg "[81] Test pick.ph"=0A= dspck_dsti pick.ph, 0x0, 0x0, 0x0, 0x0=0A= dspck_dsti pick.ph, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_dsti pick.ph, 0xffffffff, 0xffffffff, 0x0, 0x3000000=0A= dspck_dsti pick.ph, 0xffff, 0xffffffff, 0x0, 0x1000000=0A= dspck_dsti pick.ph, 0xffff0000, 0xffffffff, 0x0, 0x2000000=0A= =0A= writemsg "[82] Test packrl.ph"=0A= dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x00000000, 0x0, 0x0=0A= dspck_dstio packrl.ph, 0x0000ffff, 0x00000000, 0xffff0000, 0x0, 0x0=0A= dspck_dstio packrl.ph, 0x00000000, 0x00000000, 0x0000ffff, 0x0, 0x0=0A= dspck_dstio packrl.ph, 0x00005555, 0x00000000, 0x5555aaaa, 0x0, 0x0=0A= dspck_dstio packrl.ph, 0x0000aaaa, 0x00000000, 0xaaaa5555, 0x0, 0x0=0A= =0A= writemsg "[83] Test extr.w"=0A= dspck_atsaio extr.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsaio extr.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x80000= 0=0A= dspck_atsaio extr.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0=0A= dspck_atsaio extr.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsaio extr.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[84] Test extr_r.w"=0A= dspck_atsaio extr_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsaio extr_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000=0A= dspck_atsaio extr_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0= =0A= dspck_atsaio extr_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsaio extr_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[85] Test extr_rs.w"=0A= dspck_atsaio extr_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsaio extr_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x80= 0000=0A= dspck_atsaio extr_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0= =0A= dspck_atsaio extr_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0= =0A= dspck_atsaio extr_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[86] Test extr_s.h"=0A= dspck_atsaio extr_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsaio extr_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000= =0A= dspck_atsaio extr_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000= =0A= dspck_atsaio extr_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsaio extr_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000=0A= =0A= writemsg "[87] Test extrv_s.h"=0A= dspck_atsio extrv_s.h, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsio extrv_s.h, 0x7fffffff, 0xcbcdef01 0x7fff, 0x1f, 0x0, 0x800000= =0A= dspck_atsio extrv_s.h, 0x3fffffff, 0x2bcdef01 0x7fff, 0x1f, 0x0, 0x800000= =0A= dspck_atsio extrv_s.h, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsio extrv_s.h, 0x0, 0xfffffffe 0x7fff, 0x1, 0x0, 0x800000=0A= =0A= writemsg "[88] Test extrv.w"=0A= dspck_atsio extrv.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsio extrv.w, 0x7fffffff, 0xcbcdef01 0xffffffff, 0x1f, 0x0, 0x80000= 0=0A= dspck_atsio extrv.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0=0A= dspck_atsio extrv.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsio extrv.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[89] Test extrv_r.w"=0A= dspck_atsio extrv_r.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsio extrv_r.w, 0x7fffffff, 0xcbcdef01 0x0, 0x1f, 0x0, 0x800000=0A= dspck_atsio extrv_r.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0= =0A= dspck_atsio extrv_r.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0=0A= dspck_atsio extrv_r.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[90] Test extrv_rs.w"=0A= dspck_atsio extrv_rs.w, 0x0, 0x0 0x0, 0x0, 0x0, 0x0=0A= dspck_atsio extrv_rs.w, 0x7fffffff, 0xcbcdef01 0x7fffffff, 0x1f, 0x0, 0x80= 0000=0A= dspck_atsio extrv_rs.w, 0x3fffffff, 0x2bcdef01 0x7ffffffe, 0x1f, 0x0, 0x0= =0A= dspck_atsio extrv_rs.w, 0xffffffff, 0xffffffff 0xffffffff, 0x0, 0x0, 0x0= =0A= dspck_atsio extrv_rs.w, 0x0, 0xfffffffe 0x7fffffff, 0x1, 0x0, 0x0=0A= =0A= writemsg "[91] Test extp"=0A= dspck_tasiimom extp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f=0A= dspck_tasiimom extp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x= 4000=0A= dspck_tasiim extp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f=0A= dspck_tasiim extp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f=0A= =0A= writemsg "[92] Test extpv"=0A= dspck_tasimom extpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x0, 0x403f=0A= dspck_tasimom extpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, 0x= 4000=0A= dspck_tasim extpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f=0A= dspck_tasim extpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f=0A= =0A= writemsg "[93] Test extpdp"=0A= dspck_tasiimom extpdp, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f=0A= dspck_tasiimom extpdp, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, = 0x4000=0A= dspck_tasiim extpdp, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f=0A= dspck_tasiim extpdp, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f=0A= =0A= writemsg "[94] Test extpdpv"=0A= dspck_tasimom extpdpv, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x403f, 0x3f, 0x403f=0A= dspck_tasimom extpdpv, 0xffffffff, 0xffff7eff, 0x7e, 0x7, 0xf, 0x3f, 0x0, = 0x4000=0A= dspck_tasim extpdpv, 0xfffffff7, 0xefffffff, 0x7e, 0x7, 0x23, 0x3f=0A= dspck_tasim extpdpv, 0xffff7eff, 0xffffffff, 0x7e, 0x7, 0x2f, 0x3f=0A= =0A= writemsg "[95] Test shilo"=0A= dspck_asaio shilo, 0x0, 0x0, 0x0, 0x0, 0, 0x0, 0x0=0A= dspck_asaio shilo, 0x1, 0x80000000, 0x1, 0x80000000, 0, 0x0, 0x0=0A= dspck_asaio shilo, 0x1, 0x80000000, 0x3, 0x0, -1, 0x0, 0x0=0A= dspck_asaio shilo, 0x1, 0x80000000, 0x6, 0x0, -2, 0x0, 0x0=0A= dspck_asaio shilo, 0x1, 0x80000000, 0x18, 0x0, -4, 0x0, 0x0=0A= =0A= writemsg "[96] Test shilov"=0A= dspck_asio shilov, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0=0A= dspck_asio shilov, 0x1, 0x80000000, 0x1, 0x80000000, 0x0, 0x0, 0x0=0A= dspck_asio shilov, 0x1, 0x80000000, 0x3, 0x0, 0xffffffff, 0x0, 0x0=0A= dspck_asio shilov, 0x1, 0x80000000, 0x6, 0x0, 0xfffffffe, 0x0, 0x0=0A= dspck_asio shilov, 0x1, 0x80000000, 0x18, 0x0, 0xfffffffc, 0x0, 0x0=0A= =0A= writemsg "[97] Test mthlip"=0A= dspck_saio mthlip, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20=0A= dspck_saio mthlip, 0x0, 0x1, 0x1, 0x2, 0x2, 0x8, 0x28=0A= dspck_saio mthlip, 0xffffffff, 0xffff1234, 0xffff1234, 0xfffffffe, 0xfffff= ffe, 0x10, 0x30=0A= dspck_saio mthlip, 0xdeadbeef, 0x1234, 0x1234, 0xbeefdead, 0xbeefdead, 0x1= 8, 0x38=0A= =0A= writemsg "[98] Test wrdsp"=0A= dspck_wrdsp 0x0, 0x0, 0x0, 0x0=0A= dspck_wrdsp 0x4000, 0x20, 0x0, 0x4000=0A= dspck_wrdsp 0xffffffff, 0x3f, 0x0, 0x0fff7fbf=0A= dspck_wrdsp 0x3f, 0x1, 0x0, 0x3f=0A= dspck_wrdsp 0x1f80, 0x2, 0x0, 0x1f80=0A= =0A= writemsg "[99] Test rddsp"=0A= dspck_rddsp 0x0, 0x0, 0x0=0A= dspck_rddsp 0x0, 0x0, 0xffffffff=0A= dspck_rddsp 0x3f, 0x1, 0xffffffff=0A= dspck_rddsp 0x1f80, 0x2, 0x0fff7fbf=0A= dspck_rddsp 0x2000, 0x4, 0x0fff7fbf=0A= =0A= writemsg "[100] Test lbux"=0A= .data=0A= mydata:=0A= .byte 0x12=0A= .byte 0x34=0A= .byte 0x56=0A= .byte 0x78=0A= .byte 0x9a=0A= .byte 0xbc=0A= .byte 0xde=0A= .byte 0xf0=0A= .previous=0A= dspck_load lbux, 0x12, 0x0, mydata=0A= dspck_load lbux, 0x34, 0x1, mydata=0A= dspck_load lbux, 0x56, 0x2, mydata=0A= dspck_load lbux, 0x78, 0x3, mydata=0A= dspck_load lbux, 0x9a, 0x4, mydata=0A= dspck_load lbux, 0xbc, 0x5, mydata=0A= dspck_load lbux, 0xde, 0x6, mydata=0A= dspck_load lbux, 0xf0, 0x7, mydata=0A= =0A= writemsg "[101] Test lhx"=0A= .data=0A= myhdata:=0A= .hword 0x1234=0A= .hword 0x5678=0A= .hword 0x9abc=0A= .hword 0xdef0=0A= .previous=0A= dspck_load lhx, 0x1234, 0x0, myhdata=0A= dspck_load lhx, 0x5678, 0x2, myhdata=0A= dspck_load lhx, 0xffff9abc, 0x4, myhdata=0A= dspck_load lhx, 0xffffdef0, 0x6, myhdata=0A= =0A= writemsg "[102] Test lwx"=0A= .data=0A= mywdata:=0A= .word 0x12345678=0A= .word 0x9abcdef0=0A= .word 0x13579abc=0A= .word 0xffff0001=0A= .previous=0A= dspck_load lwx, 0x12345678, 0x0, mywdata=0A= dspck_load lwx, 0x9abcdef0, 0x4, mywdata=0A= dspck_load lwx, 0x13579abc, 0x8, mywdata=0A= dspck_load lwx, 0xffff0001, 0xc, mywdata=0A= =0A= writemsg "[103] Test bposge32"=0A= dspck_bposge32 0x0, 0=0A= dspck_bposge32 0x1f, 0=0A= dspck_bposge32 0x20, 1=0A= dspck_bposge32 0x3f, 1=0A= =0A= pass=0A= .end DIAG=0A= =0A= ------=_NextPart_000_000A_01C5CE74.255828F0 Content-Type: application/octet-stream; name="utils-dsp.inc" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="utils-dsp.inc" Content-length: 10174 # MIPS DSP ASE simulator testsuite utility functions.=0A= # Copyright (C) 2005 Free Software Foundation, Inc.=0A= # Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu.=0A= #=0A= # This file is part of the GNU simulators.=0A= #=0A= # This program is free software; you can redistribute it and/or modify=0A= # it under the terms of the GNU General Public License as published by=0A= # the Free Software Foundation; either version 2, or (at your option)=0A= # any later version.=0A= #=0A= # This program is distributed in the hope that it will be useful,=0A= # but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= # GNU General Public License for more details.=0A= #=0A= # You should have received a copy of the GNU General Public License along= =0A= # with this program; if not, write to the Free Software Foundation, Inc.,= =0A= # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */=0A= =0A= # $4, $5, $6, $7, $ac0, $ac1, $ac2, $ac3 are used as temps by the macros=0A= # defined here.=0A= =0A= # If a !=3D b, jump to _fail.=0A= # Otherwise, fall through.=0A= .macro dsp_assert a, b=0A= beq \a, \b, 1f=0A= nop=0A= j _fail=0A= nop=0A= 1:=20=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, s, t)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_dstio inst, d, s, t, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \s=0A= li $5, \t=0A= \inst $6, $4, $5=0A= li $7, \d=0A= dsp_assert $6, $7=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # (inst s, t)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_stio inst, s, t, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \s=0A= li $5, \t=0A= \inst $4, $5=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, s, t)=0A= .macro dspck_dsti inst, d, s, t, crin=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \s=0A= li $5, \t=0A= \inst $6, $4, $5=0A= li $7, \d=0A= dsp_assert $6, $7=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if tou =3D=3D (inst tin, s)=0A= .macro dspck_tsi inst, tou, tin, s, crin=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \s=0A= li $5, \tin=0A= \inst $5, $4=0A= li $6, \tou=0A= dsp_assert $5, $6=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, imm)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_dIio inst, d, imm, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= \inst $5, \imm=0A= li $6, \d=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, s)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_dsio inst, d, s, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \s=0A= \inst $6, $4=0A= li $7, \d=0A= dsp_assert $6, $7=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, t, sa)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_dtsaio inst, d, t, sa, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \t=0A= \inst $6, $4, \sa=0A= li $7, \d=0A= dsp_assert $6, $7=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (inst ?, t, sa)=0A= .macro dspck_dtsai inst, d, t, sa, crin=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \t=0A= \inst $6, $4, \sa=0A= li $7, \d=0A= dsp_assert $6, $7=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac3 <=3D {hiin, loin}=0A= # (inst $ac3, s, t)=0A= # Check if {hiou, loou} =3D=3D $ac3=0A= # Check if (crout & 0x80000) =3D=3D (dsp control register & 0x80000)=0A= .macro dspck_astio inst, hiin, loin, hiou, loou, s, t, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hiin=0A= mthi $4, $ac3=0A= li $4, \loin=0A= mtlo $4, $ac3=0A= li $4, \s=0A= li $5, \t=0A= \inst $ac3, $4, $5=0A= li $4, \hiou=0A= mfhi $5, $ac3=0A= dsp_assert $4, $5=0A= li $4, \loou=0A= mflo $5, $ac3=0A= dsp_assert $4, $5=0A= li $4, \crout=0A= and $4, $4, 0x80000=0A= rddsp $5=0A= and $5, $5, 0x80000=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac1 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac1, sa)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_atsaio inst, hi, lo, t, sa, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac1=0A= li $4, \lo=0A= mtlo $4, $ac1=0A= \inst $5, $ac1, \sa=0A= li $6, \t=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac1 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac1, s)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_atsio inst, hi, lo, t, s, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac1=0A= li $4, \lo=0A= mtlo $4, $ac1=0A= li $4, \s=0A= \inst $5, $ac1, $4=0A= li $6, \t=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D (crin & crinmask)=0A= # Set $ac2 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac2, size)=0A= # Check if (crout & croutmask) =3D=3D (dsp control register & croutmask)= =0A= .macro dspck_tasiimom inst, hi, lo, t, size, crin, crinmask, crout, croutm= ask=0A= li $4, \crin=0A= and $4, \crinmask=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac2=0A= li $4, \lo=0A= mtlo $4, $ac2=0A= \inst $5, $ac2, \size=0A= li $6, \t=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= and $4, \croutmask=0A= rddsp $5=0A= and $5, \croutmask=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D (crin & crinmask)=0A= # Set $ac2 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac2, size)=0A= .macro dspck_tasiim inst, hi, lo, t, size, crin, crinmask=0A= li $4, \crin=0A= and $4, \crinmask=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac2=0A= li $4, \lo=0A= mtlo $4, $ac2=0A= \inst $5, $ac2, \size=0A= li $6, \t=0A= dsp_assert $5, $6=0A= .endm=0A= =0A= # Set dsp control register <=3D (crin & crinmask)=0A= # Set $ac2 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac2, s)=0A= # Check if (crout & croutmask) =3D=3D (dsp control register & croutmask)= =0A= .macro dspck_tasimom inst, hi, lo, t, s, crin, crinmask, crout, croutmask= =0A= li $4, \crin=0A= and $4, \crinmask=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac2=0A= li $4, \lo=0A= mtlo $4, $ac2=0A= li $4, \s=0A= \inst $5, $ac2, $4=0A= li $6, \t=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= and $4, \croutmask=0A= rddsp $5=0A= and $5, \croutmask=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D (crin & crinmask)=0A= # Set $ac2 <=3D {hi, lo}=0A= # Check if t =3D=3D (inst ? $ac2, s)=0A= .macro dspck_tasim inst, hi, lo, t, s, crin, crinmask=0A= li $4, \crin=0A= and $4, \crinmask=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac2=0A= li $4, \lo=0A= mtlo $4, $ac2=0A= li $4, \s=0A= \inst $5, $ac2, $4=0A= li $6, \t=0A= dsp_assert $5, $6=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac0 <=3D {hi, lo}=0A= # (inst $ac0, shift)=0A= # Check if $ac0 =3D=3D {hio, loo}=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_asaio inst, hi, lo, hio, loo, shift, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac0=0A= li $4, \lo=0A= mtlo $4, $ac0=0A= \inst $ac0, \shift=0A= mfhi $5, $ac0=0A= li $6, \hio=0A= dsp_assert $5, $6=0A= mflo $5, $ac0=0A= li $6, \loo=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac0 <=3D {hi, lo}=0A= # (inst $ac0, s)=0A= # Check if $ac0 =3D=3D {hio, loo}=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_asio inst, hi, lo, hio, loo, s, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac0=0A= li $4, \lo=0A= mtlo $4, $ac0=0A= li $4, \s=0A= \inst $ac0, $4=0A= mfhi $5, $ac0=0A= li $6, \hio=0A= dsp_assert $5, $6=0A= mflo $5, $ac0=0A= li $6, \loo=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Set $ac3 <=3D {hi, lo}=0A= # Check if s =3D=3D (inst ? $ac3)=0A= # Check if $ac3 =3D=3D {hio, loo}=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_saio inst, hi, lo, hio, loo, s, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $4, \hi=0A= mthi $4, $ac3=0A= li $4, \lo=0A= mtlo $4, $ac3=0A= li $5, \s=0A= \inst $5, $ac3=0A= mfhi $5, $ac3=0A= li $6, \hio=0A= dsp_assert $5, $6=0A= mflo $5, $ac3=0A= li $6, \loo=0A= dsp_assert $5, $6=0A= li $4, \crout=0A= rddsp $5=0A= dsp_assert $4, $5=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # (wrdsp s, m)=0A= # Check if crout =3D=3D dsp control register=0A= .macro dspck_wrdsp s, m, crin, crout=0A= li $4, \crin=0A= wrdsp $4=0A= li $5, \s=0A= wrdsp $5, \m=0A= li $6, \crout=0A= rddsp $7=0A= dsp_assert $6, $7=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if d =3D=3D (rddsp ?, m)=0A= .macro dspck_rddsp d, m, crin=0A= li $4, \crin=0A= wrdsp $4=0A= rddsp $5, \m=0A= li $6, \d=0A= dsp_assert $5, $6=0A= .endm=0A= =0A= # Check if d =3D=3D (inst i(b))=0A= .macro dspck_load inst, d, i, b=0A= li $4, \i=0A= la $5, \b=0A= \inst $6, $4($5)=0A= li $7, \d=0A= dsp_assert $6, $7=0A= .endm=0A= =0A= # Set dsp control register <=3D crin=0A= # Check if bposge32 is taken or not as expected in r=0A= # (1 =3D> taken, 0 =3D> not taken)=0A= .macro dspck_bposge32 crin, r=0A= li $4, \crin=0A= wrdsp $4=0A= li $5, 1=0A= bposge32 1f=0A= nop=0A= li $5, 0=0A= 1:=0A= li $6, \r=0A= dsp_assert $5, $6=0A= .endm=0A= ------=_NextPart_000_000A_01C5CE74.255828F0--