Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.10
diff -c -3 -p -r1.10 Makefile.in
*** mips/Makefile.in	16 May 2003 07:11:42 -0000	1.10
--- mips/Makefile.in	11 Oct 2005 21:40:21 -0000
*************** SIM_OBJS = \
*** 47,52 ****
--- 47,53 ----
  	cp1.o \
  	interp.o \
  	mdmx.o \
+ 	dsp.o \
  	sim-main.o \
  	sim-hload.o \
  	sim-engine.o \
*************** cp1.o: $(srcdir)/cp1.c config.h sim-main
*** 78,83 ****
--- 79,86 ----
  
  mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
  
+ dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
+ 
  multi-run.o: multi-include.h tmp-mach-multi
  
  ../igen/igen:
*************** IGEN_INCLUDE=\
*** 94,99 ****
--- 97,103 ----
  	$(srcdir)/sb1.igen \
  	$(srcdir)/tx.igen \
  	$(srcdir)/vr.igen \
+ 	$(srcdir)/dsp.igen \
  
  # NB:	Since these can be built by a number of generators, care
  #	must be taken to ensure that they are only dependant on
Index: mips/configure.ac
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.ac,v
retrieving revision 1.5
diff -c -3 -p -r1.5 configure.ac
*** mips/configure.ac	16 Jun 2005 15:15:49 -0000	1.5
--- mips/configure.ac	11 Oct 2005 21:40:21 -0000
*************** case "${target}" in
*** 146,164 ****
  			sim_m16_filter="16"
  			;;
    mipsisa32r2*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips32r2,mips16,mips16e"
  			sim_m16_machine="-M mips16,mips16e,mips32r2"
  			sim_igen_filter="32,f"
  			sim_mach_default="mipsisa32r2"
  			;;
    mipsisa32*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips32,mips16,mips16e"
  			sim_m16_machine="-M mips16,mips16e,mips32"
  			sim_igen_filter="32,f"
  			sim_mach_default="mipsisa32"
  			;;
    mipsisa64r2*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e"
  			sim_m16_machine="-M mips16,mips16e,mips64r2"
  			sim_igen_filter="32,64,f"
  			sim_mach_default="mipsisa64r2"
--- 146,164 ----
  			sim_m16_filter="16"
  			;;
    mipsisa32r2*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips32r2,mips16,mips16e,dsp"
  			sim_m16_machine="-M mips16,mips16e,mips32r2"
  			sim_igen_filter="32,f"
  			sim_mach_default="mipsisa32r2"
  			;;
    mipsisa32*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips32,mips16,mips16e,dsp"
  			sim_m16_machine="-M mips16,mips16e,mips32"
  			sim_igen_filter="32,f"
  			sim_mach_default="mipsisa32"
  			;;
    mipsisa64r2*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,dsp"
  			sim_m16_machine="-M mips16,mips16e,mips64r2"
  			sim_igen_filter="32,64,f"
  			sim_mach_default="mipsisa64r2"
*************** case "${target}" in
*** 169,175 ****
  			sim_mach_default="mips_sb1"
  			;;
    mipsisa64*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips64,mips3d,mips16,mips16e"
  			sim_m16_machine="-M mips16,mips16e,mips64"
  			sim_igen_filter="32,64,f"
  			sim_mach_default="mipsisa64"
--- 169,175 ----
  			sim_mach_default="mips_sb1"
  			;;
    mipsisa64*-*-*)	sim_gen=M16
! 		        sim_igen_machine="-M mips64,mips3d,mips16,mips16e,dsp"
  			sim_m16_machine="-M mips16,mips16e,mips64"
  			sim_igen_filter="32,64,f"
  			sim_mach_default="mipsisa64"
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.59
diff -c -3 -p -r1.59 mips.igen
*** mips/mips.igen	16 Jun 2005 15:15:49 -0000	1.59
--- mips/mips.igen	11 Oct 2005 21:40:21 -0000
***************
*** 71,76 ****
--- 71,77 ----
  :model:::mips16e:mips16e:		// m16e.igen
  :model:::mips3d:mips3d:			// mips3d.igen
  :model:::mdmx:mdmx:			// mdmx.igen
+ :model:::dsp:dsp:			// dsp.igen
  
  //  Vendor Extensions
  //
***************
*** 2477,2486 ****
  *mipsIII:
  *mipsIV:
  *mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
  *vr4100:
  *vr5000:
  *r3900:
--- 2478,2483 ----
***************
*** 2505,2514 ****
  *mipsIII:
  *mipsIV:
  *mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
  *vr4100:
  *vr5000:
  *r3900:
--- 2502,2507 ----
***************
*** 2607,2616 ****
  *mipsIII:
  *mipsIV:
  *mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
  *vr4100:
  *vr5000:
  *r3900:
--- 2600,2605 ----
***************
*** 2628,2637 ****
  *mipsIII:
  *mipsIV:
  *mipsV:
- *mips32:
- *mips32r2:
- *mips64:
- *mips64r2:
  *vr4100:
  *vr5000:
  *r3900:
--- 2617,2622 ----
***************
*** 5697,5700 ****
--- 5682,5686 ----
  :include:::sb1.igen
  :include:::tx.igen
  :include:::vr.igen
+ :include:::dsp.igen
  
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.27
diff -c -3 -p -r1.27 sim-main.h
*** mips/sim-main.h	12 May 2004 01:42:33 -0000	1.27
--- mips/sim-main.h	11 Oct 2005 21:40:21 -0000
*************** struct _sim_cpu {
*** 312,318 ****
     state. */
  
  #ifndef TM_MIPS_H
! #define LAST_EMBED_REGNUM (89)
  #define NUM_REGS (LAST_EMBED_REGNUM + 1)
  
  #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
--- 312,318 ----
     state. */
  
  #ifndef TM_MIPS_H
! #define LAST_EMBED_REGNUM (96)
  #define NUM_REGS (LAST_EMBED_REGNUM + 1)
  
  #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
*************** struct _sim_cpu {
*** 349,354 ****
--- 349,399 ----
  #define DEPC	(REGISTERS[87])
  #define EPC	(REGISTERS[88])
  
+ #define AC0LOIDX	(33)	/* Must be the same register as LO */
+ #define AC0HIIDX	(34)	/* Must be the same register as HI */
+ #define AC1LOIDX	(90)
+ #define AC1HIIDX	(91)
+ #define AC2LOIDX	(92)
+ #define AC2HIIDX	(93)
+ #define AC3LOIDX	(94)
+ #define AC3HIIDX	(95)
+ 
+ #define DSPLO(N)	(REGISTERS[DSPLO_REGNUM[N]])
+ #define DSPHI(N)	(REGISTERS[DSPHI_REGNUM[N]])
+ 
+ #define DSPCRIDX	(96)	/* DSP control register */
+ #define DSPCR		(REGISTERS[DSPCRIDX])
+ 
+ #define DSPCR_POS_SHIFT		(0)
+ #define DSPCR_POS_MASK		(0x3f)
+ #define DSPCR_POS_SMASK		(DSPCR_POS_MASK << DSPCR_POS_SHIFT)
+ 
+ #define DSPCR_SCOUNT_SHIFT	(7)
+ #define DSPCR_SCOUNT_MASK	(0x3f)
+ #define DSPCR_SCOUNT_SMASK	(DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
+ 
+ #define DSPCR_CARRY_SHIFT	(13)
+ #define DSPCR_CARRY_MASK	(1)
+ #define DSPCR_CARRY_SMASK	(DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
+ #define DSPCR_CARRY		(1 << DSPCR_CARRY_SHIFT)
+ 
+ #define DSPCR_EFI_SHIFT		(14)
+ #define DSPCR_EFI_MASK		(1)
+ #define DSPCR_EFI_SMASK		(DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
+ #define DSPCR_EFI		(1 << DSPCR_EFI_MASK)
+ 
+ #define DSPCR_OUFLAG_SHIFT	(16)
+ #define DSPCR_OUFLAG_MASK	(0xff)
+ #define DSPCR_OUFLAG_SMASK	(DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
+ #define DSPCR_OUFLAG4		(1 << (DSPCR_OUFLAG_SHIFT + 4))
+ #define DSPCR_OUFLAG5		(1 << (DSPCR_OUFLAG_SHIFT + 5))
+ #define DSPCR_OUFLAG6		(1 << (DSPCR_OUFLAG_SHIFT + 6))
+ #define DSPCR_OUFLAG7		(1 << (DSPCR_OUFLAG_SHIFT + 7))
+ 
+ #define DSPCR_CCOND_SHIFT	(24)
+ #define DSPCR_CCOND_MASK	(0xf)
+ #define DSPCR_CCOND_SMASK	(DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
+ 
    /* All internal state modified by signal_exception() that may need to be
       rolled back for passing moment-of-exception image back to gdb. */
    unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
*************** INLINE_SIM_MAIN (unsigned16) ifetch16 PA
*** 933,938 ****
--- 978,986 ----
  void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
  extern FILE *tracefh;
  
+ extern int DSPLO_REGNUM[4];
+ extern int DSPHI_REGNUM[4];
+ 
  INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
  extern SIM_CORE_SIGNAL_FN mips_core_signal;
  
Index: testsuite/sim/mips/basic.exp
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/mips/basic.exp,v
retrieving revision 1.5
diff -c -3 -p -r1.5 basic.exp
*** testsuite/sim/mips/basic.exp	11 Apr 2004 06:28:08 -0000	1.5
--- testsuite/sim/mips/basic.exp	11 Oct 2005 21:40:21 -0000
*************** if {[istarget mips*-elf] && [board_info 
*** 71,74 ****
--- 71,76 ----
  
      run_sim_test mdmx-ob.s $submodels
      run_sim_test mdmx-ob-sb1.s $submodels
+ 
+     run_sim_test mips32-dsp.s $models
  }
