[lttng-dev] RCU on non-cache-coherent memory

[lttng-dev] RCU on non-cache-coherent memory

[Yuxin Ren]

Hi all,

Is there any research or publications about RCU on top of
non-cache-coherent multi-core architecture?
Not only RCU, any other synchronization technique on top of
non-cache-coherent multi-core
is also helpful.

Thanks a lot!
Yuxin

[lttng-dev] RCU on non-cache-coherent memory

[Mathieu Desnoyers]

----- On Aug 1, 2016, at 8:30 PM, Yuxin Ren ryx at gwmail.gwu.edu wrote:

> Hi all,
> 
> Is there any research or publications about RCU on top of
> non-cache-coherent multi-core architecture?
> Not only RCU, any other synchronization technique on top of
> non-cache-coherent multi-core
> is also helpful.

CCing Paul E. McKenney, who might know more on this topic.

Back in 2009 when I started the liburcu.org project, I
planned to eventually add support for such architectures,
e.g. Blackfin, which is why I initially added the cmm_mc(),
cmm_rmc() and cmm_wmc() macros in the library (see
CONFIG_HAVE_MEM_COHERENCY). However, all currently implemented
architectures have mem coherency, so it's always defined as a
simple compiler barrier. See include/urcu/arch/generic.h in liburcu
for details.

Thanks,

Mathieu

> 
> Thanks a lot!
> Yuxin
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> lttng-dev mailing list
> lttng-dev at lists.lttng.org
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-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com

[lttng-dev] RCU on non-cache-coherent memory

[Paul E. McKenney]

On Tue, Aug 02, 2016 at 10:58:57PM +0000, Mathieu Desnoyers wrote:
> ----- On Aug 1, 2016, at 8:30 PM, Yuxin Ren ryx at gwmail.gwu.edu wrote:
> 
> > Hi all,
> > 
> > Is there any research or publications about RCU on top of
> > non-cache-coherent multi-core architecture?
> > Not only RCU, any other synchronization technique on top of
> > non-cache-coherent multi-core
> > is also helpful.
> 
> CCing Paul E. McKenney, who might know more on this topic.
> 
> Back in 2009 when I started the liburcu.org project, I
> planned to eventually add support for such architectures,
> e.g. Blackfin, which is why I initially added the cmm_mc(),
> cmm_rmc() and cmm_wmc() macros in the library (see
> CONFIG_HAVE_MEM_COHERENCY). However, all currently implemented
> architectures have mem coherency, so it's always defined as a
> simple compiler barrier. See include/urcu/arch/generic.h in liburcu
> for details.

Mathieu pretty much covered it.  We only have theoretical experience
with non-cache-coherent systems.  You might want to contact the authors
of these papers:

http://www.sigops.org/sosp/sosp11/posters/summaries/sosp11-final7.pdf
http://arxiv.org/pdf/1301.4490.pdf

There are probably others, as this was a hot topic a couple of years ago.

							Thanx, Paul