From mboxrd@z Thu Jan  1 00:00:00 1970
From: mathieu.desnoyers@efficios.com (Mathieu Desnoyers)
Date: Tue, 2 Aug 2016 22:58:57 +0000 (UTC)
Subject: [lttng-dev] RCU on non-cache-coherent memory
In-Reply-To: <CAAKbDrfJ=umcdwFp7j5RDMZt7AfhAhCnmOfZqvD2WeNuhcb0rw@mail.gmail.com>
References: <CAAKbDrfJ=umcdwFp7j5RDMZt7AfhAhCnmOfZqvD2WeNuhcb0rw@mail.gmail.com>
Message-ID: <1648244903.1131.1470178737812.JavaMail.zimbra@efficios.com>

----- On Aug 1, 2016, at 8:30 PM, Yuxin Ren ryx at gwmail.gwu.edu wrote:

> Hi all,
> 
> Is there any research or publications about RCU on top of
> non-cache-coherent multi-core architecture?
> Not only RCU, any other synchronization technique on top of
> non-cache-coherent multi-core
> is also helpful.

CCing Paul E. McKenney, who might know more on this topic.

Back in 2009 when I started the liburcu.org project, I
planned to eventually add support for such architectures,
e.g. Blackfin, which is why I initially added the cmm_mc(),
cmm_rmc() and cmm_wmc() macros in the library (see
CONFIG_HAVE_MEM_COHERENCY). However, all currently implemented
architectures have mem coherency, so it's always defined as a
simple compiler barrier. See include/urcu/arch/generic.h in liburcu
for details.

Thanks,

Mathieu

> 
> Thanks a lot!
> Yuxin
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-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com