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* Implimenting MIPS R4650 DWATCH register as hbreak hardware breakpoint
@ 1999-04-04 11:25 M. David Gelbman
  1999-04-04 13:03 ` M. David Gelbman
  0 siblings, 1 reply; 4+ messages in thread
From: M. David Gelbman @ 1999-04-04 11:25 UTC (permalink / raw)
  To: gdb

Anybody,

I'm developing an application on a an IDT MIPS R4650 based board.  this
MIPS CPU has a DWATCH register capable of breaking on a data read or
write (or both).

What must I do to the host portion of GDB to let it know my target is
capable of implimenting a "hardware" breakpoint?  Further what must I do
to modify my target GDB stub?

I suspect the host part is simply a re-configuration of somthing in the
.gdbini file.  I expect that the target stub needs to parse a new
command in handle_exception() through the "target remote" protocol.  But
I haven't yet found the magic words.

-- 

Sincerely,

M. David Gelbman, Senior Software Engineer
Network Peripherals, Inc.                   <NASDAQ:NPIX>
4170 Veteran's Memorial Highway,  Bohemia,  NY 11716-1009
516.737.2363 (voice)   516.737.2372 (FAX)  ftp://per_need
whois:mdg  mailto:dgelbman@npiny.com  http://www.npix.com


^ permalink raw reply	[flat|nested] 4+ messages in thread
[parent not found: <3707AE48.2582E501.cygnus.gdb@npiny.com>]

end of thread, other threads:[~1999-04-13 21:36 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
1999-04-04 11:25 Implimenting MIPS R4650 DWATCH register as hbreak hardware breakpoint M. David Gelbman
1999-04-04 13:03 ` M. David Gelbman
     [not found] <3707AE48.2582E501.cygnus.gdb@npiny.com>
1999-04-13 20:42 ` Andrew Cagney
1999-04-13 21:36   ` Jason Molenda

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