From: Palmer Dabbelt <palmer@sifive.com>
To: Jim Wilson <jimw@sifive.com>, Tim Newsome <tim@sifive.com>
Cc: gdb-patches@sourceware.org, andrew.burgess@embecosm.com,
Jim Wilson <jimw@sifive.com>
Subject: Re: [PATCH] RISC-V: Correct legacy misa register number.
Date: Wed, 04 Jul 2018 00:35:00 -0000 [thread overview]
Message-ID: <mhng-9ebd3260-e59a-4deb-a76f-bda705114eb4@palmer-si-x1c4> (raw)
In-Reply-To: <20180704001334.27460-1-jimw@sifive.com>
On Tue, 03 Jul 2018 17:13:34 PDT (-0700), Jim Wilson wrote:
> The main purpose of this patch is to fix the legacy misa register number, which
> is missing the +65 added to all of the other CSRs.
>
> This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of
> RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c.
>
> I don't have access to legacy hardware that I can test the misa number change
> with, but it has been tested on a riscv64-linux system using patched gdb and
> patched kernel, since it isn't usable otherwise.
FWIW, there's no legacy RISC-V hardware that can run a native GDB. Thus the
only mechanism to access this would be via a JTAG debugger, and there's no ABI
spec for those.
Is there even a reason to have a legacy MISA CSR exposed to GDB? I feel like
we can just handle this in the JTAG debugger and keep this oddity from slipping
into an ABI.
I'm adding Tim as he might have more context.
> Jim
>
> gdb/
> * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of
> RISCV_LAST_FP_REGNUM + 1.
> (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
> ---
> gdb/riscv-tdep.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
> index ab5e278759..4fc05976ba 100644
> --- a/gdb/riscv-tdep.h
> +++ b/gdb/riscv-tdep.h
> @@ -39,11 +39,11 @@ enum
> RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
>
> RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
> -#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
> +#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> RISCV_LAST_CSR_REGNUM = 4160,
> - RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10,
> + RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
>
> RISCV_PRIV_REGNUM = 4161,
If we can't nuke RISCV_CSR_LEGACY_MISA_REGNUM them I'm fine with either way.
Sorry to keep throwing a wrench in the works :)
next prev parent reply other threads:[~2018-07-04 0:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-04 0:14 Jim Wilson
2018-07-04 0:35 ` Palmer Dabbelt [this message]
2018-07-04 16:17 ` Jim Wilson
2018-07-06 3:16 ` Tim Newsome
[not found] ` <20180704083410.GD2675@embecosm.com>
2018-07-16 22:01 ` Jim Wilson
2018-07-17 15:40 ` Andrew Burgess
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