Re: [PATCH] RISC-V: Correct legacy misa register number.

[Andrew Burgess <andrew.burgess@embecosm.com>]

* Jim Wilson <jimw@sifive.com> [2018-07-16 15:01:41 -0700]:

> On Wed, Jul 4, 2018 at 1:34 AM, Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > * Jim Wilson <jimw@sifive.com> [2018-07-03 17:13:34 -0700]:
> >
> >> The main purpose of this patch is to fix the legacy misa register number, which
> >> is missing the +65 added to all of the other CSRs.
> >>
> >> This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of
> >> RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c.
> >>
> >> I don't have access to legacy hardware that I can test the misa number change
> >> with, but it has been tested on a riscv64-linux system using patched gdb and
> >> patched kernel, since it isn't usable otherwise.
> >>
> >> Jim
> >>
> >>       gdb/
> >>       * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of
> >>       RISCV_LAST_FP_REGNUM + 1.
> >>       (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
> >
> > Regardless of the discussion about RISCV_CSR_LEGACY_MISA_REGNUM
> > could you push the change to DECLARE_CSR anyway please.  I think this
> > is a good clean up and it's unrelated to the other change.
> 
> Tim Newsome confirmed that there should be no special behavior in
> OpenOCD to handle the legacy misa register number.  I'd like approval
> to commit the whole patch.  It is a bug fix for live code, and a minor
> consistency cleanup.

I approve then :)

Thanks,

Andrew