[PATCH] RISC-V: Correct legacy misa register number.

[Jim Wilson <jimw@sifive.com>]

The main purpose of this patch is to fix the legacy misa register number, which
is missing the +65 added to all of the other CSRs.

This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of
RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c.

I don't have access to legacy hardware that I can test the misa number change
with, but it has been tested on a riscv64-linux system using patched gdb and
patched kernel, since it isn't usable otherwise.

Jim

	gdb/
	* riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of
	RISCV_LAST_FP_REGNUM + 1.
	(RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
---
 gdb/riscv-tdep.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index ab5e278759..4fc05976ba 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -39,11 +39,11 @@ enum
   RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */
 
   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
-#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
+#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
 #include "opcode/riscv-opc.h"
 #undef DECLARE_CSR
   RISCV_LAST_CSR_REGNUM = 4160,
-  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10,
+  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
 
   RISCV_PRIV_REGNUM = 4161,
 
-- 
2.17.1