From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78992 invoked by alias); 4 Jul 2018 00:35:26 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 78969 invoked by uid 89); 4 Jul 2018 00:35:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=throwing, HX-Received:sk:a2-v6mr, Hx-spam-relays-external:209.85.160.65, H*RU:209.85.160.65 X-HELO: mail-pl0-f65.google.com Received: from mail-pl0-f65.google.com (HELO mail-pl0-f65.google.com) (209.85.160.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Jul 2018 00:35:22 +0000 Received: by mail-pl0-f65.google.com with SMTP id w8-v6so1789167ply.8 for ; Tue, 03 Jul 2018 17:35:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=J+LK2jvJbI9Poi9Ksrl3fq07J7xM7bASDkhC3CY15E0=; b=kp4i8SyhlLdwf61E2nIZau3oNp6xbDuLsjU7bDLez8F4Tb6gE/1mX8TpeCnZC0rp9a x4W/1qDkVoGUZskVINu7CcC94m811R3abOl+mD8Gf6Qkh7WQvtHeyToTdtzZRNmG2y8e yiOfwXQwXAWUGA8jFzKSPIlOy5aScOaOj+4mmEaGfIvv+bFuT9YJZnwWlEejzxwrnKP8 IztWLxho0AYFe/dxInvaYrMjATxemEXLTAXT0tz9qtHXWdKnmAn/IYr0ry2fTd3hyJ02 SeEjCw1Vg02CQJMFP/8U16xIjv8bAr1ZOYY4ThyJ0R2DhQcocoS7TUOByTCsqTAMgMEc YDBQ== Return-Path: Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 133-v6sm3990706pfu.158.2018.07.03.17.35.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Jul 2018 17:35:19 -0700 (PDT) Date: Wed, 04 Jul 2018 00:35:00 -0000 X-Google-Original-Date: Tue, 03 Jul 2018 17:27:33 PDT (-0700) Subject: Re: [PATCH] RISC-V: Correct legacy misa register number. In-Reply-To: <20180704001334.27460-1-jimw@sifive.com> CC: gdb-patches@sourceware.org, andrew.burgess@embecosm.com, Jim Wilson From: Palmer Dabbelt To: Jim Wilson , Tim Newsome Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-07/txt/msg00065.txt.bz2 On Tue, 03 Jul 2018 17:13:34 PDT (-0700), Jim Wilson wrote: > The main purpose of this patch is to fix the legacy misa register number, which > is missing the +65 added to all of the other CSRs. > > This also changes DECLARE_CSR to use RISCV_FIRST_CSR_REGNUM instead of > RISCV_LAST_FP_REGNUM+1 to be consistent with riscv-tdep.c. > > I don't have access to legacy hardware that I can test the misa number change > with, but it has been tested on a riscv64-linux system using patched gdb and > patched kernel, since it isn't usable otherwise. FWIW, there's no legacy RISC-V hardware that can run a native GDB. Thus the only mechanism to access this would be via a JTAG debugger, and there's no ABI spec for those. Is there even a reason to have a legacy MISA CSR exposed to GDB? I feel like we can just handle this in the JTAG debugger and keep this oddity from slipping into an ABI. I'm adding Tim as he might have more context. > Jim > > gdb/ > * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of > RISCV_LAST_FP_REGNUM + 1. > (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM. > --- > gdb/riscv-tdep.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h > index ab5e278759..4fc05976ba 100644 > --- a/gdb/riscv-tdep.h > +++ b/gdb/riscv-tdep.h > @@ -39,11 +39,11 @@ enum > RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ > > RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ > -#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num, > +#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, > #include "opcode/riscv-opc.h" > #undef DECLARE_CSR > RISCV_LAST_CSR_REGNUM = 4160, > - RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10, > + RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM, > > RISCV_PRIV_REGNUM = 4161, If we can't nuke RISCV_CSR_LEGACY_MISA_REGNUM them I'm fine with either way. Sorry to keep throwing a wrench in the works :)