Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default

[Pedro Alves <palves@redhat.com>]

On 10/08/2018 03:37 PM, Paul Koning wrote:
> 
> 
>> On Oct 8, 2018, at 10:25 AM, Joel Brobecker <brobecker@adacore.com> wrote:
>>
>>> [...] coupled with the fact that I'm not sure
>>> whether there are in fact implementations of riscv that trigger
>>> watchpoints after the write, makes me wonder, do we really need this?
>>
>> Actually - that's a very good point. Do we know of any architecture
>> where the watchpoint triggers after the write?
> 
> I think MIPS is one.  The documentation is not entirely clear but that's what I remember from using it.
x86 is another.  But my question is -- do we know of any RISC-V
implementation that triggers after the write, given that the spec
says it should trigger before the write.

Thanks,
Pedro Alves