From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 34385 invoked by alias); 8 Oct 2018 14:42:18 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 34365 invoked by uid 89); 8 Oct 2018 14:42:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_PASS autolearn=no version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 08 Oct 2018 14:42:16 +0000 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 96DC0311C3D3; Mon, 8 Oct 2018 14:42:15 +0000 (UTC) Received: from [127.0.0.1] (ovpn04.gateway.prod.ext.ams2.redhat.com [10.39.146.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 603F7308BDA1; Mon, 8 Oct 2018 14:42:14 +0000 (UTC) Subject: Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default To: Paul Koning , Joel Brobecker References: <20180917103409.GJ5952@embecosm.com> <77978648-c391-0011-6c03-c7fd38429914@embecosm.com> <20181003223703.GA22933@adacore.com> <20181008095839.GC5952@embecosm.com> <4c4c1369-0f5c-549a-ed82-51563c5e6dd6@redhat.com> <20181008142533.GA2993@adacore.com> <5019D845-3AEB-4287-A8BD-D9F96F5755B7@comcast.net> Cc: Andrew Burgess , Craig Blackmore , gdb-patches@sourceware.org From: Pedro Alves Message-ID: Date: Mon, 08 Oct 2018 14:42:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <5019D845-3AEB-4287-A8BD-D9F96F5755B7@comcast.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-10/txt/msg00176.txt.bz2 On 10/08/2018 03:37 PM, Paul Koning wrote: > > >> On Oct 8, 2018, at 10:25 AM, Joel Brobecker wrote: >> >>> [...] coupled with the fact that I'm not sure >>> whether there are in fact implementations of riscv that trigger >>> watchpoints after the write, makes me wonder, do we really need this? >> >> Actually - that's a very good point. Do we know of any architecture >> where the watchpoint triggers after the write? > > I think MIPS is one. The documentation is not entirely clear but that's what I remember from using it. x86 is another. But my question is -- do we know of any RISC-V implementation that triggers after the write, given that the spec says it should trigger before the write. Thanks, Pedro Alves