Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default

[Craig Blackmore <craig.blackmore@embecosm.com>]

On 08/10/18 15:51, Joel Brobecker wrote:
>>> I think MIPS is one.  The documentation is not entirely clear but
>>> that's what I remember from using it.
>> x86 is another.  But my question is -- do we know of any RISC-V
>> implementation that triggers after the write, given that the spec
>> says it should trigger before the write.
I don't know of any RISC-V implementations that trigger after the write.
The debug spec has 'suggested breakpoint timings' but the triggers are
allowed to fire at whatever point is most convenient for the implementation.

I suggest that Joel's earlier patch
(https://sourceware.org/ml/gdb-patches/2018-09/msg00821.html) be
upstreamed so that things work for the majority of systems. We can
handle implementations with other timings later, if they appear.

Thanks,
Craig

> That was what I meant as well; I agree with Pedro that we don't
> really need to do anything fancy if:
>   - the spec's recommendation is to trigger before the write
>   - and we don't know of any system that decided to go against
>     the recommendation.
> The day we discover a system that does in fact go against the
> recommendation, we can simply deal with it then and decide what
> the best course of action is.
>