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From: Jim Wilson <jimw@sifive.com>
To: Andrew Burgess <andrew.burgess@embecosm.com>
Cc: gdb-patches@sourceware.org, Palmer Dabbelt <palmer@sifive.com>
Subject: Re: [PATCH 2/4] gdb/riscv: Extend instruction decode to cover more instructions
Date: Wed, 29 Aug 2018 22:05:00 -0000	[thread overview]
Message-ID: <CAFyWVaY0BkyxvqFwV3PTb0i5wG+s4rGT4H1zJrtyr3U1WaGwGA@mail.gmail.com> (raw)
In-Reply-To: <d74de1fc1f7150666bee412ba9d48e5357c3316e.1535560591.git.andrew.burgess@embecosm.com>

On Wed, Aug 29, 2018 at 9:40 AM, Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> +      else if (xlen < 16 && is_c_addi4spn_insn (ival))
> +       {
> +         m_opcode = ADDI;
> +         m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
> +         m_rs1 = RISCV_SP_REGNUM;
> +         m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
> +       }

c.addi4spn is always valid.  I don't think that there should be a xlen
check here.

> +      else if (is_c_sdsp_insn (ival))
> +       decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));

c.sdsp is only valid for RV64I and RV128I.  For RV32I this is a
c.fswsp instruction.  So there needs to be a xlen != 4 check here

Jim


  reply	other threads:[~2018-08-29 22:05 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-29 16:41 [PATCH 0/4] RISCV Non-DWARF stack unwinding Andrew Burgess
2018-08-29 16:41 ` [PATCH 1/4] gdb/riscv: remove extra caching of misa register Andrew Burgess
2018-08-29 23:10   ` Palmer Dabbelt
2018-08-29 16:41 ` [PATCH 2/4] gdb/riscv: Extend instruction decode to cover more instructions Andrew Burgess
2018-08-29 22:05   ` Jim Wilson [this message]
2018-08-29 23:10   ` Palmer Dabbelt
2018-08-29 16:41 ` [PATCH 3/4] gdb: Extend the trad-frame API Andrew Burgess
2018-08-31 15:03   ` Tom Tromey
2018-08-29 16:41 ` [PATCH 4/4] gdb/riscv: Provide non-DWARF stack unwinder Andrew Burgess
2018-08-29 23:36   ` Palmer Dabbelt
2018-08-29 23:36 ` [PATCH 0/4] RISCV Non-DWARF stack unwinding Palmer Dabbelt

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