From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4733 invoked by alias); 29 Aug 2018 22:05:21 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 4174 invoked by uid 89); 29 Aug 2018 22:05:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr1-f68.google.com Received: from mail-wr1-f68.google.com (HELO mail-wr1-f68.google.com) (209.85.221.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Aug 2018 22:05:19 +0000 Received: by mail-wr1-f68.google.com with SMTP id v17-v6so6186630wrr.9 for ; Wed, 29 Aug 2018 15:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0cTsO4bMUrnzAEXy39NyuQCVRGVyfW1nnW3j4qD+qmc=; b=nGoL2yWQH8pxdGPotZhmjCQszW9aMm5xBksiCn1aITruryf7WmTYOzdNvzNpX8KrE0 QGx63qQHbh2SakdGSwbUs0v5yYLgjZC72jp8K7rA6FgMvHn+hO1Ol9drvHvkPB4bdAg3 Tb/1CtSJ4HdSomnKAInPhgIqkEyYSHxnfrYLYnXyWDhFLC1PZ0eWdIQnq3BbqMTTqfGV dUAlZvxWP/RcbX2NDqn/vnLR19JnVw8TQN60STWhgsnNgSahMwqVqssoKASZowfxMmcw DwCkeOgu2maEc74Y1gXcz1mxYw+Gn30N2yukDj/YccHpF2bB+tCsl8rJvQvXw/+9v9qc YVEA== MIME-Version: 1.0 Received: by 2002:adf:e40f:0:0:0:0:0 with HTTP; Wed, 29 Aug 2018 15:05:16 -0700 (PDT) In-Reply-To: References: From: Jim Wilson Date: Wed, 29 Aug 2018 22:05:00 -0000 Message-ID: Subject: Re: [PATCH 2/4] gdb/riscv: Extend instruction decode to cover more instructions To: Andrew Burgess Cc: gdb-patches@sourceware.org, Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-08/txt/msg00784.txt.bz2 On Wed, Aug 29, 2018 at 9:40 AM, Andrew Burgess wrote: > + else if (xlen < 16 && is_c_addi4spn_insn (ival)) > + { > + m_opcode = ADDI; > + m_rd = decode_register_index_short (ival, OP_SH_CRS2S); > + m_rs1 = RISCV_SP_REGNUM; > + m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); > + } c.addi4spn is always valid. I don't think that there should be a xlen check here. > + else if (is_c_sdsp_insn (ival)) > + decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); c.sdsp is only valid for RV64I and RV128I. For RV32I this is a c.fswsp instruction. So there needs to be a xlen != 4 check here Jim