From: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>
To: Thiago Jung Bauermann <thiago.bauermann@linaro.org>,
Luis <luis.machado.foss@gmail.com>,
GDB Patches <gdb-patches@sourceware.org>
Cc: "guinevere@redhat.com" <guinevere@redhat.com>,
Ezra Sitorus <Ezra.Sitorus@arm.com>,
Matthieu Longo <Matthieu.Longo@arm.com>,
"simark@simark.ca" <simark@simark.ca>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v3 1/5] [PATCH 1/5] gdb/aarch64: Add POR_EL0 register support for FEAT_S1POE
Date: Fri, 7 Aug 2026 19:51:55 +0000 [thread overview]
Message-ID: <AS8PR08MB10099C30174429EDE2AC594659BD12@AS8PR08MB10099.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <87tspmkiy4.fsf@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 10704 bytes --]
Hi,
>On 25/07/2026 07:13, Thiago Jung Bauermann wrote:
>> Srinath Parvathaneni <Srinath.Parvathaneni@arm.com> writes:
>>
>>>>> * p/x $por_el0
>>>>> * set $por_el0 = <value>
>>>>>
>>>>> Example:
>>>>> (gdb) info register por_el0
>>>>> por_el0 0x7 [ P15=--- P14=--- P13=--- P12=--- P11=--- P10=--- P9=--- P8=--- P7=---
>>> P6=--- P5=--- P4=--- P3=--- P2=--- P1=--- P0=rwx ]
>>>>> (gdb) set $por_el0=0xffffffff77777777
>>>>> (gdb) info register por_el0
>>>>> por_el0 0xffffffff77777777 [ P15=??? P14=??? P13=??? P12=??? P11=??? P10=??? P9=???
>>> P8=??? P7=rwx P6=rwx P5=rwx P4=rwx P3=rwx P2=rwx P1=rwx P0=rwx ]
>>>>> (gdb) p $por_el0
>>>>> $1 = [ P15=??? P14=??? P13=??? P12=??? P11=??? P10=??? P9=??? P8=??? P7=rwx P6=rwx
>>> P5=rwx P4=rwx P3=rwx P2=rwx P1=rwx P0=rwx ]
>>>>> (gdb) p/x $por_el0
>>>>> $2 = 0xffffffff77777777
>>>>> (gdb) set $por_el0=0x57
>>>>> (gdb) info register por_el0
>>>>> por_el0 0x57 [ P15=--- P14=--- P13=--- P12=--- P11=--- P10=--- P9=--- P8=--- P7=---
>>> P6=--- P5=--- P4=--- P3=--- P2=--- P1=rw- P0=rwx ]
>>>>> (gdb) set $por_el0=0xf7f7f7f7f7f7f7f7
>>>>> (gdb) info register por_el0
>>>>> por_el0 0xf7f7f7f7f7f7f7f7 [ P15=??? P14=rwx P13=??? P12=rwx P11=??? P10=rwx P9=???
>>> P8=rwx P7=??? P6=rwx P5=??? P4=rwx P3=??? P2=rwx P1=??? P0=rwx ]
>>>>> (gdb)
>>>>
>>>> Looking at the output above I think it is a bit hard to read.
>>
>> I think part of the reason for it being hard to read is that the output
>> is very wide.
>
>Indeed. I mean, as an overview it's fine. But it really depends on the
>most common use case for this register.
>
>What I want to steer clear from is something like we have for SVE
>registers. It is a barrage of text that isn´t very easy to use.
>
>>
>> One way to address this is Srinath's suggestion below to not print
>> zeroed keys. Another would be to improve the output of the flag type to
>> add line breaks when the terminal's width is reached, as is done when
>> printing array values.
>>
>> Another option would be to use a struct rather than a flags type. Then
>> there would be one type per field, and it would be possible to display
>> (and set) only one key.
>>
>> Not sure which of them I prefer. The struct idea has the advantage of
>> letting the user easily set protection keys individually. OTOH it's
>> not printed isn a very compact way.
>>
>> If easily displaying/setting individual keys isn't that important, I
>> think I slightly prefer not printing zeroed keys as Srinath suggests,
>> possibly coupled with adding line breaks when the line is too long, to
>> address the case of having many keys set in the register.
>>
>
>Good suggestions. I'd say if users want...
>
>- An overview with permissions, then print what we have above
>- To use it as a mask, we should have the raw value
>- To read/write individual P<x> entries within the register, then we
>should have pseudo-registers that map back to por_el0.
>
>The pseudo registers would leave the interpretation of the raw values
>out of the XML, therefore remote stubs wouldn´t need to pass that sort
>of information.
>
>Stretching it a little bit, remote stubs could even send a modified
>version of these fields in the XML and gdb would start printing
>something else.
>
Hi Luis/Thiago,
After looking at the suggestions in the thread, I made a few changes to the
POR_EL0 interface. The custom display for por_el0 has been updated, and I've
also added support for pseudo registers for the individual permission fields.
Could you please have a look at the output below? If this looks ok, I'll re-spin
the series, address the remaining review comments and send it out for another
review.
Also added a new group (por) for por_el0 register along with poe pseduo registers.
Set 1:
(gdb) info register por_el0
por_el0 0x0000000000000077 [ P1=rwx P0=rwx ]
(gdb) info register por
por_el0 0x0000000000000077 [ P1=rwx P0=rwx ]
por_el0_p0 0x7 rwx
por_el0_p1 0x7 rwx
por_el0_p2 0x0 ---
por_el0_p3 0x0 ---
por_el0_p4 0x0 ---
por_el0_p5 0x0 ---
por_el0_p6 0x0 ---
por_el0_p7 0x0 ---
por_el0_p8 0x0 ---
por_el0_p9 0x0 ---
por_el0_p10 0x0 ---
por_el0_p11 0x0 ---
por_el0_p12 0x0 ---
por_el0_p13 0x0 ---
por_el0_p14 0x0 ---
por_el0_p15 0x0 ---
Set 2:
(gdb) set $por_el0=0xf7f7f7f7f7f7f7f7
(gdb) info register por_el0
por_el0 0xf7f7f7f7f7f7f7f7 [ P15=??? P14=rwx P13=??? P12=rwx
P11=??? P10=rwx P9=??? P8=rwx
P7=??? P6=rwx P5=??? P4=rwx
P3=??? P2=rwx P1=??? P0=rwx ]
(gdb) info register por
por_el0 0xf7f7f7f7f7f7f7f7 [ P15=??? P14=rwx P13=??? P12=rwx
P11=??? P10=rwx P9=??? P8=rwx
P7=??? P6=rwx P5=??? P4=rwx
P3=??? P2=rwx P1=??? P0=rwx ]
por_el0_p0 0x7 rwx
por_el0_p1 0xf ???
por_el0_p2 0x7 rwx
por_el0_p3 0xf ???
por_el0_p4 0x7 rwx
por_el0_p5 0xf ???
por_el0_p6 0x7 rwx
por_el0_p7 0xf ???
por_el0_p8 0x7 rwx
por_el0_p9 0xf ???
por_el0_p10 0x7 rwx
por_el0_p11 0xf ???
por_el0_p12 0x7 rwx
por_el0_p13 0xf ???
por_el0_p14 0x7 rwx
por_el0_p15 0xf ???
Set 3:
(gdb) set $por_el0=0x0123456789abcdef
(gdb) info register por_el0
por_el0 0x0123456789abcdef [ P14=r-- P13=--x P12=r-x P11=-w-
P10=rw- P9=-wx P8=rwx P7=???
P6=??? P5=??? P4=??? P3=???
P2=??? P1=??? P0=??? ]
(gdb) info register por
por_el0 0x0123456789abcdef [ P14=r-- P13=--x P12=r-x P11=-w-
P10=rw- P9=-wx P8=rwx P7=???
P6=??? P5=??? P4=??? P3=???
P2=??? P1=??? P0=??? ]
por_el0_p0 0xf ???
por_el0_p1 0xe ???
por_el0_p2 0xd ???
por_el0_p3 0xc ???
por_el0_p4 0xb ???
por_el0_p5 0xa ???
por_el0_p6 0x9 ???
por_el0_p7 0x8 ???
por_el0_p8 0x7 rwx
por_el0_p9 0x6 -wx
por_el0_p10 0x5 rw-
por_el0_p11 0x4 -w-
por_el0_p12 0x3 r-x
por_el0_p13 0x2 --x
por_el0_p14 0x1 r--
por_el0_p15 0x0 ---
(gdb)
Set 4:
(gdb) set $por_el0=0x7
(gdb) info register por
por_el0 0x0000000000000007 [ P0=rwx ]
por_el0_p0 0x7 rwx
por_el0_p1 0x0 ---
por_el0_p2 0x0 ---
por_el0_p3 0x0 ---
por_el0_p4 0x0 ---
por_el0_p5 0x0 ---
por_el0_p6 0x0 ---
por_el0_p7 0x0 ---
por_el0_p8 0x0 ---
por_el0_p9 0x0 ---
por_el0_p10 0x0 ---
por_el0_p11 0x0 ---
por_el0_p12 0x0 ---
por_el0_p13 0x0 ---
por_el0_p14 0x0 ---
por_el0_p15 0x0 ---
(gdb) set $por_el0_p1=0x7
(gdb) set $por_el0_p3=0x5
(gdb) set $por_el0_p4=0x3
(gdb) set $por_el0_p5=0x1
(gdb) set $por_el0_p6=0xf
(gdb) info register por
por_el0 0x000000000f135077 [ P6=??? P5=r-- P4=r-x P3=rw-
P1=rwx P0=rwx ]
por_el0_p0 0x7 rwx
por_el0_p1 0x7 rwx
por_el0_p2 0x0 ---
por_el0_p3 0x5 rw-
por_el0_p4 0x3 r-x
por_el0_p5 0x1 r--
por_el0_p6 0xf ???
por_el0_p7 0x0 ---
por_el0_p8 0x0 ---
por_el0_p9 0x0 ---
por_el0_p10 0x0 ---
por_el0_p11 0x0 ---
por_el0_p12 0x0 ---
por_el0_p13 0x0 ---
por_el0_p14 0x0 ---
por_el0_p15 0x0 ---
(gdb)
Please let me know your comments, thanks.
Regards,
Sri.
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next prev parent reply other threads:[~2026-08-07 19:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-14 20:15 [PATCH v3 0/5] " srinath.parvathaneni
2026-07-14 20:15 ` [PATCH v3 1/5] [PATCH 1/5] " srinath.parvathaneni
2026-07-21 19:53 ` Luis
2026-07-25 6:20 ` Thiago Jung Bauermann
2026-07-25 7:37 ` Luis
2026-07-25 18:44 ` Thiago Jung Bauermann
2026-08-07 19:51 ` Srinath Parvathaneni [this message]
2026-08-11 23:23 ` Thiago Jung Bauermann
2026-08-12 21:33 ` Luis
2026-08-12 21:32 ` Luis
2026-07-21 20:25 ` Luis
2026-07-23 9:29 ` Srinath Parvathaneni
2026-07-25 6:13 ` Thiago Jung Bauermann
2026-07-25 7:29 ` Luis
2026-07-14 20:15 ` [PATCH v3 2/5] [PATCH 2/5] gdb: Improve SIGSEGV diagnostics for POE faults srinath.parvathaneni
2026-07-21 20:30 ` Luis
2026-07-22 9:41 ` Matthieu Longo
2026-07-22 23:11 ` Luis
2026-07-23 9:03 ` Srinath Parvathaneni
2026-07-25 7:39 ` Luis
2026-07-14 20:15 ` [PATCH v3 3/5] [PATCH 3/5] gdbserver/aarch64: Add POR_EL0 register support srinath.parvathaneni
2026-07-14 20:15 ` [PATCH v3 4/5] [PATCH 4/5] gdb/aarch64: Add core file support for FEAT_S1POE srinath.parvathaneni
2026-07-21 20:14 ` Luis
2026-07-14 20:15 ` [PATCH v3 5/5] [PATCH 5/5] gdb/testsuite: Add FEAT_S1POE testcases srinath.parvathaneni
2026-07-21 20:38 ` Luis
2026-07-25 6:23 ` Thiago Jung Bauermann
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