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From: "Metzger, Markus T" <markus.t.metzger@intel.com>
To: Pierre Marsais <pierre.marsais@lse.epita.fr>,
	"gdb-patches@sourceware.org"	<gdb-patches@sourceware.org>
Subject: RE: [PATCH] Add support for recording xsave x86 instruction
Date: Thu, 27 Sep 2018 08:45:00 -0000	[thread overview]
Message-ID: <A78C989F6D9628469189715575E55B236B35E55E@IRSMSX104.ger.corp.intel.com> (raw)
In-Reply-To: <20180921003827.1525-1-pierre.marsais@lse.epita.fr>

Hello Pierre,

> +        case 4: /* xsave */

We should also check MOD != 3.


> +          uint64_t tmpu64;
> +          if (i386_record_lea_modrm_addr (&ir, &tmpu64))
> +            return -1;
> +          if (record_full_arch_list_add_mem (tmpu64, 512 + 64))
> +            return -1;
> +
> +          for (int i = 2; i < 64; i++) {
> +            if (!((1 << i) & tdep->xcr0))
> +              continue;
> +
> +            unsigned int size, offset, tmp1, tmp2;
> +
> +            if (!__get_cpuid_count(0xd, i, &size, &offset, &tmp1, &tmp2))
> +              return -1;

This would check the native configuration, correct?  What if we recorded
remotely on a different x86 box?

Also I think that we would need to check the inferior architecture to handle
32-bit compatibility mode.

SIZE may be zero.  We should probably check that and continue.  I'm not sure
whether we can actually run into this case but it doesn't hurt to check.

Nit: there's a space before (.


> +
> +            if (record_full_arch_list_add_mem (tmpu64 + offset, size))
> +              return -1;

Looks like this assumes the standard (non-compacted) XSAVE format.

For the compacted format, the offset must be computed by accumulating
the sizes of preceding components.


> diff --git a/gdb/testsuite/gdb.reverse/i386-xsave-reverse.c
> b/gdb/testsuite/gdb.reverse/i386-xsave-reverse.c

> +void xsave_test(void) {

Nit: space before (.


> +	char buf[4096] __attribute__ ((aligned (64))) = { 0 };

The test could query the XSAVE buffer size.


> +	asm ("xor %%eax, %%eax\n\t"
> +	     "not %%eax\n\t"
> +	     "mov %%eax, %%edx\n\t"
> +	     "xsave %0":"=m"(buf) ::"eax", "edx"); } /* end xsave_test */

The } should probably go onto the next line.


> +if ![istarget "*86*-*linux*"] then {
> +    verbose "Skipping i386 reverse tests."
> +    return
> +}

Why exclude 64-bit?


> +runto main

You'd typically check whether that succeeds and abort the test if it doesn't.


> +if [supports_process_record] {
> +    # Activate process record/replay
> +    gdb_test_no_output "record" "turn on process record"
> +}

Shouldn't we abort the test if record is not supported?


> +gdb_test "reverse-step" "xor.*" "reverse-step to xsave"
> +
> +gdb_test "print buf" ".* = '\\\\000' <repeats 4095 times>" \
> +    "verify xsave buffer after reverse xsave"

Regards,
Markus.
Intel Deutschland GmbH
Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Christin Eisenschmid, Christian Lamprechter
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928


  reply	other threads:[~2018-09-27  8:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21  0:38 Pierre Marsais
2018-09-27  8:45 ` Metzger, Markus T [this message]
2018-10-01  0:25   ` Pierre Marsais
2018-10-01  6:58     ` Metzger, Markus T
2018-10-03  0:05       ` Pierre Marsais
2018-10-01  0:29 ` [PATCH v2] " Pierre Marsais
2018-10-02 23:55 ` [PATCH v3] " Pierre Marsais
     [not found]   ` <CAMe9rOqTeGBckegskZLKxJJL-aexTiorLTEbL2kps_KjJs20Rg@mail.gmail.com>
2018-10-06  0:20     ` Pierre Marsais
2018-10-06  0:16 ` [PATCH v4 1/3] " Pierre Marsais
2018-10-06  0:16   ` [PATCH v4 2/3] Do not mistreat instructions as cmpxchg8b Pierre Marsais
2018-10-11 11:56     ` Metzger, Markus T
2018-10-06  0:16   ` [PATCH v4 3/3] Add support for recording xsavec x86 instruction Pierre Marsais

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