From: Yao Qi <qiyaoltc@gmail.com>
To: Alan Hayward <Alan.Hayward@arm.com>
Cc: "gdb-patches\@sourceware.org" <gdb-patches@sourceware.org>,
nd <nd@arm.com>
Subject: Re: [PATCH 2/11] Add IA64_MAX_REGISTER_SIZE
Date: Wed, 05 Apr 2017 10:00:00 -0000 [thread overview]
Message-ID: <8637dnqils.fsf@gmail.com> (raw)
In-Reply-To: <B65C3EF7-3E91-4044-83A1-DD681C5422DF@arm.com> (Alan Hayward's message of "Tue, 4 Apr 2017 10:12:13 +0000")
Alan Hayward <Alan.Hayward@arm.com> writes:
Hi Alan,
We have to define such macro if we have no other ways to remove
MAX_REGISTER_SIZE. AFAIK, there are some ways to remove many usages of
MAX_REGISTER_SIZE.
> @@ -1516,7 +1516,7 @@ examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc,
> else if (qp == 0 && rN == 2
> && ((rM == fp_reg && fp_reg != 0) || rM == 12))
> {
> - gdb_byte buf[MAX_REGISTER_SIZE];
> + gdb_byte buf[IA64_MAX_REGISTER_SIZE];
> CORE_ADDR saved_sp = 0;
> /* adds r2, spilloffset, rFramePointer
> or
"buf" is used in the code below,
get_frame_register (this_frame, sp_regnum, buf);
saved_sp = extract_unsigned_integer (buf, 8, byte_order);
why don't we use get_frame_register_unsigned, so the "buf" can be
removed completely.
saved_sp = get_frame_register_unsigned (this_frame, sp_regnum);
> @@ -2289,7 +2289,7 @@ static struct value *
> ia64_sigtramp_frame_prev_register (struct frame_info *this_frame,
> void **this_cache, int regnum)
> {
> - gdb_byte buf[MAX_REGISTER_SIZE];
> + gdb_byte buf[IA64_MAX_REGISTER_SIZE];
>
"buf" is used in the code below,
read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
pc = extract_unsigned_integer (buf, 8, byte_order);
so it is for IP register. Its size is 8-byte, so we can move "buf"
here,
gdb_byte buf[8];
read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
pc = extract_unsigned_integer (buf, sizeof (buf), byte_order);
> struct gdbarch *gdbarch = get_frame_arch (this_frame);
> enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
> @@ -2495,7 +2495,7 @@ ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
> struct gdbarch *gdbarch = get_frame_arch (this_frame);
> enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
> long new_sof, old_sof;
> - gdb_byte buf[MAX_REGISTER_SIZE];
> + gdb_byte buf[IA64_MAX_REGISTER_SIZE];
>
Use get_frame_register_{,un}signed, so we can remove "buf" completely.
> /* We never call any libunwind routines that need to write registers. */
> gdb_assert (!write);
> @@ -2575,7 +2575,7 @@ ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum,
> struct gdbarch *gdbarch = get_regcache_arch (regcache);
> enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
> long new_sof, old_sof;
> - gdb_byte buf[MAX_REGISTER_SIZE];
> + gdb_byte buf[IA64_MAX_REGISTER_SIZE];
>
"buf" is used
regcache_cooked_read (regcache, IA64_IP_REGNUM, buf);
ip = extract_unsigned_integer (buf, 8, byte_order);
so we can use regcache_cooked_read_unsigned,
regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &ip);
> /* We never call any libunwind routines that need to write registers. */
> gdb_assert (!write);
> @@ -2982,7 +2982,7 @@ ia64_libunwind_frame_prev_register (struct frame_info *this_frame,
> {
> int rrb_pr = 0;
> ULONGEST cfm;
> - gdb_byte buf[MAX_REGISTER_SIZE];
> + gdb_byte buf[IA64_MAX_REGISTER_SIZE];
>
Use get_frame_register_unsigned.
> /* Fetch predicate register rename base from current frame
> marker for this frame. */
The only leftover of MAX_REGISTER_SIZE is about floating type
conversion, in ia64_register_to_value, ia64_push_dummy_call, etc. Then,
we can define an macro for the size of floating types, and replace
MAX_REGISTER_SIZE with it.
--
Yao (齐尧)
next prev parent reply other threads:[~2017-04-05 10:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-04 10:12 Alan Hayward
2017-04-05 10:00 ` Yao Qi [this message]
2017-04-11 12:47 ` Alan Hayward
2017-04-11 17:17 ` Yao Qi
2017-04-12 13:41 ` Alan Hayward
2017-04-25 16:08 ` Yao Qi
2017-04-26 10:38 ` Alan Hayward
2017-04-27 10:17 ` Yao Qi
2017-04-27 10:48 ` Alan Hayward
[not found] ` <79E51549-1B65-4DA8-891A-17EF061E03A3@arm.com>
2017-06-06 10:04 ` Yao Qi
2017-06-06 12:57 ` Alan Hayward
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