* [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers
@ 2020-11-26 9:20 Przemyslaw Wirkus via Gdb-patches
2020-11-26 12:06 ` Luis Machado via Gdb-patches
0 siblings, 1 reply; 3+ messages in thread
From: Przemyslaw Wirkus via Gdb-patches @ 2020-11-26 9:20 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 1298 bytes --]
This patch updates FPCR (Floating-point Control Register) and FPSR
(Floating-point Status Register) named fields in AArch64. For detailed
description of named register FPCR and FPSR bit fields see [1] and [2].
Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
FPCR are defined starting from Armv8.7 architecture.
[1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
[2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr
Example:
$ cat -n test.c
1 float foo(float pi, float r) {
2 return pi * r * r;
3 }
4
5 int main() {
6 foo(3.14, 1.725);
7 return 0;
8 }
$ gcc -O0 -g3 test.c -o test
Before patch (step to line 7):
>>> info all-registers fpsr
fpsr 0x10 16
>>> info all-registers fpcr
fpcr 0x0 0
After patch:
>>> info all-registers fpsr
fpsr 0x10 [ IXC ]
>>> info all-registers fpcr
fpcr 0x0 [ RMode=0 ]
OK for master ?
gdb/ChangeLog:
2020-11-25 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
* features/aarch64-fpu.xml: Add named FPCR and FPSR register bit-fields.
[-- Attachment #2: rb13709.patch --]
[-- Type: application/octet-stream, Size: 6639 bytes --]
diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
index 87e394656fccc5803456d358cc147efe52dd2ebc..5b636a5f4d20c4e9092d0f4b6762b69e0aa0cfce 100644
--- a/gdb/features/aarch64-fpu.c
+++ b/gdb/features/aarch64-fpu.c
@@ -99,6 +99,35 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
field_type = tdesc_named_type (feature, "vnq");
tdesc_add_field (type_with_fields, "q", field_type);
+ type_with_fields = tdesc_create_flags (feature, "fpsr_flags", 4);
+ tdesc_add_flag (type_with_fields, 0, "IOC");
+ tdesc_add_flag (type_with_fields, 1, "DZC");
+ tdesc_add_flag (type_with_fields, 2, "OFC");
+ tdesc_add_flag (type_with_fields, 3, "UFC");
+ tdesc_add_flag (type_with_fields, 4, "IXC");
+ tdesc_add_flag (type_with_fields, 7, "IDC");
+ tdesc_add_flag (type_with_fields, 27, "QC");
+ tdesc_add_flag (type_with_fields, 28, "V");
+ tdesc_add_flag (type_with_fields, 29, "C");
+ tdesc_add_flag (type_with_fields, 30, "Z");
+ tdesc_add_flag (type_with_fields, 31, "N");
+
+ type_with_fields = tdesc_create_flags (feature, "fpcr_flags", 4);
+ tdesc_add_flag (type_with_fields, 0, "FIZ");
+ tdesc_add_flag (type_with_fields, 1, "AH");
+ tdesc_add_flag (type_with_fields, 2, "NEP");
+ tdesc_add_flag (type_with_fields, 8, "IOE");
+ tdesc_add_flag (type_with_fields, 9, "DZE");
+ tdesc_add_flag (type_with_fields, 10, "OFE");
+ tdesc_add_flag (type_with_fields, 11, "UFE");
+ tdesc_add_flag (type_with_fields, 12, "IXE");
+ tdesc_add_flag (type_with_fields, 15, "IDE");
+ tdesc_add_flag (type_with_fields, 19, "FZ16");
+ tdesc_add_bitfield (type_with_fields, "RMode", 22, 23);
+ tdesc_add_flag (type_with_fields, 24, "FZ");
+ tdesc_add_flag (type_with_fields, 25, "DN");
+ tdesc_add_flag (type_with_fields, 26, "AHP");
+
regnum = 34;
tdesc_create_reg (feature, "v0", regnum++, 1, NULL, 128, "aarch64v");
tdesc_create_reg (feature, "v1", regnum++, 1, NULL, 128, "aarch64v");
@@ -132,7 +161,7 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
tdesc_create_reg (feature, "v29", regnum++, 1, NULL, 128, "aarch64v");
tdesc_create_reg (feature, "v30", regnum++, 1, NULL, 128, "aarch64v");
tdesc_create_reg (feature, "v31", regnum++, 1, NULL, 128, "aarch64v");
- tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "int");
- tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "fpsr", regnum++, 1, NULL, 32, "fpsr_flags");
+ tdesc_create_reg (feature, "fpcr", regnum++, 1, NULL, 32, "fpcr_flags");
return regnum;
}
diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
index eae763c4b412d6af53f449480c3f330c336bd353..3862f0c4f08f76cdf4fde34398200fdfe987f982 100644
--- a/gdb/features/aarch64-fpu.xml
+++ b/gdb/features/aarch64-fpu.xml
@@ -83,6 +83,76 @@
<reg name="v29" bitsize="128" type="aarch64v"/>
<reg name="v30" bitsize="128" type="aarch64v"/>
<reg name="v31" bitsize="128" type="aarch64v"/>
- <reg name="fpsr" bitsize="32"/>
- <reg name="fpcr" bitsize="32"/>
+
+ <flags id="fpsr_flags" size="4">
+ <!-- Invalid Operation cumulative floating-point exception bit. -->
+ <field name="IOC" start="0" end="0"/>
+ <!-- Divide by Zero cumulative floating-point exception bit. -->
+ <field name="DZC" start="1" end="1"/>
+ <!-- Overflow cumulative floating-point exception bit. -->
+ <field name="OFC" start="2" end="2"/>
+ <!-- Underflow cumulative floating-point exception bit. -->
+ <field name="UFC" start="3" end="3"/>
+ <!-- Inexact cumulative floating-point exception bit.. -->
+ <field name="IXC" start="4" end="4"/>
+ <!-- Input Denormal cumulative floating-point exception bit. -->
+ <field name="IDC" start="7" end="7"/>
+ <!-- Cumulative saturation bit, Advanced SIMD only. -->
+ <field name="QC" start="27" end="27"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented: Overflow condition flag for AArch32
+ floating-point comparison operations. -->
+ <field name="V" start="28" end="28"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Carry condition flag for AArch32 floating-point comparison operations.
+ -->
+ <field name="C" start="29" end="29"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Zero condition flag for AArch32 floating-point comparison operations.
+ -->
+ <field name="Z" start="30" end="30"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Negative condition flag for AArch32 floating-point comparison
+ operations. -->
+ <field name="N" start="31" end="31"/>
+ </flags>
+ <reg name="fpsr" bitsize="32" type="fpsr_flags"/>
+
+ <flags id="fpcr_flags" size="4">
+ <!-- Flush Inputs to Zero (part of Armv8.7). -->
+ <field name="FIZ" start="0" end="0"/>
+ <!-- Alternate Handling (part of Armv8.7). -->
+ <field name="AH" start="1" end="1"/>
+ <!-- Controls how the output elements other than the lowest element of the
+ vector are determined for Advanced SIMD scalar instructions (part of
+ Armv8.7). -->
+ <field name="NEP" start="2" end="2"/>
+ <!-- Invalid Operation floating-point exception trap enable. -->
+ <field name="IOE" start="8" end="8"/>
+ <!-- Divide by Zero floating-point exception trap enable. -->
+ <field name="DZE" start="9" end="9"/>
+ <!-- Overflow floating-point exception trap enable. -->
+ <field name="OFE" start="10" end="10"/>
+ <!-- Underflow floating-point exception trap enable. -->
+ <field name="UFE" start="11" end="11"/>
+ <!-- Inexact floating-point exception trap enable. -->
+ <field name="IXE" start="12" end="12"/>
+ <!-- Input Denormal floating-point exception trap enable. -->
+ <field name="IDE" start="15" end="15"/>
+ <!-- Flush-to-zero mode control bit on half-precision data-processing
+ instructions. -->
+ <field name="FZ16" start="19" end="19"/>
+ <!-- Rounding Mode control field. -->
+ <field name="RMode" start="22" end="23"/>
+ <!-- Flush-to-zero mode control bit. -->
+ <field name="FZ" start="24" end="24"/>
+ <!-- Default NaN mode control bit. -->
+ <field name="DN" start="25" end="25"/>
+ <!-- Alternative half-precision control bit. -->
+ <field name="AHP" start="26" end="26"/>
+ </flags>
+ <reg name="fpcr" bitsize="32" type="fpcr_flags"/>
</feature>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers
2020-11-26 9:20 [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers Przemyslaw Wirkus via Gdb-patches
@ 2020-11-26 12:06 ` Luis Machado via Gdb-patches
2020-11-26 12:13 ` Przemyslaw Wirkus via Gdb-patches
0 siblings, 1 reply; 3+ messages in thread
From: Luis Machado via Gdb-patches @ 2020-11-26 12:06 UTC (permalink / raw)
To: Przemyslaw Wirkus, gdb-patches
Hi,
On 11/26/20 6:20 AM, Przemyslaw Wirkus wrote:
> This patch updates FPCR (Floating-point Control Register) and FPSR
> (Floating-point Status Register) named fields in AArch64. For detailed
> description of named register FPCR and FPSR bit fields see [1] and [2].
>
> Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
> FPCR are defined starting from Armv8.7 architecture.
>
> [1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
> [2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr
>
> Example:
> $ cat -n test.c
> 1 float foo(float pi, float r) {
> 2 return pi * r * r;
> 3 }
> 4
> 5 int main() {
> 6 foo(3.14, 1.725);
> 7 return 0;
> 8 }
>
> $ gcc -O0 -g3 test.c -o test
>
> Before patch (step to line 7):
>>>> info all-registers fpsr
> fpsr 0x10 16
>>>> info all-registers fpcr
> fpcr 0x0 0
>
> After patch:
>>>> info all-registers fpsr
> fpsr 0x10 [ IXC ]
>>>> info all-registers fpcr
> fpcr 0x0 [ RMode=0 ]
>
> OK for master ?
>
> gdb/ChangeLog:
>
> 2020-11-25 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
>
> * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
> * features/aarch64-fpu.xml: Add named FPCR and FPSR register bit-fields.
>
This is OK. Thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers
2020-11-26 12:06 ` Luis Machado via Gdb-patches
@ 2020-11-26 12:13 ` Przemyslaw Wirkus via Gdb-patches
0 siblings, 0 replies; 3+ messages in thread
From: Przemyslaw Wirkus via Gdb-patches @ 2020-11-26 12:13 UTC (permalink / raw)
To: Luis Machado, gdb-patches
> > OK for master ?
> >
> > gdb/ChangeLog:
> >
> > 2020-11-25 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
> >
> > * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
> > * features/aarch64-fpu.xml: Add named FPCR and FPSR register bit-
> fields.
> >
>
> This is OK. Thanks!
commit 239ca5e497dda2c151009d664d500086a5c2173a
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-11-26 12:14 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-26 9:20 [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers Przemyslaw Wirkus via Gdb-patches
2020-11-26 12:06 ` Luis Machado via Gdb-patches
2020-11-26 12:13 ` Przemyslaw Wirkus via Gdb-patches
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox