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([2804:7f0:8284:370e:cc47:17a8:8973:691]) by smtp.gmail.com with ESMTPSA id s68sm2207904qkc.43.2020.11.26.04.06.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Nov 2020 04:06:51 -0800 (PST) Subject: Re: [PATCH][GDB] aarch64: Add named flags for FPCR and FPSR registers To: Przemyslaw Wirkus , "gdb-patches@sourceware.org" References: Message-ID: <68aed4c3-2e21-a5ad-8c14-f47d83f70c4a@linaro.org> Date: Thu, 26 Nov 2020 09:06:48 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" Hi, On 11/26/20 6:20 AM, Przemyslaw Wirkus wrote: > This patch updates FPCR (Floating-point Control Register) and FPSR > (Floating-point Status Register) named fields in AArch64. For detailed > description of named register FPCR and FPSR bit fields see [1] and [2]. > > Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in > FPCR are defined starting from Armv8.7 architecture. > > [1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr > [2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr > > Example: > $ cat -n test.c > 1 float foo(float pi, float r) { > 2 return pi * r * r; > 3 } > 4 > 5 int main() { > 6 foo(3.14, 1.725); > 7 return 0; > 8 } > > $ gcc -O0 -g3 test.c -o test > > Before patch (step to line 7): >>>> info all-registers fpsr > fpsr 0x10 16 >>>> info all-registers fpcr > fpcr 0x0 0 > > After patch: >>>> info all-registers fpsr > fpsr 0x10 [ IXC ] >>>> info all-registers fpcr > fpcr 0x0 [ RMode=0 ] > > OK for master ? > > gdb/ChangeLog: > > 2020-11-25 Przemyslaw Wirkus > > * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate. > * features/aarch64-fpu.xml: Add named FPCR and FPSR register bit-fields. > This is OK. Thanks!