This patch updates FPCR (Floating-point Control Register) and FPSR
(Floating-point Status Register) named fields in AArch64. For detailed
description of named register FPCR and FPSR bit fields see [1] and [2].

Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
FPCR are defined starting from Armv8.7 architecture.

[1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
[2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr

Example:
$ cat -n test.c
	 1  float foo(float pi, float r) {
	 2      return pi * r * r;
	 3  }
	 4
	 5  int main() {
	 6      foo(3.14, 1.725);
	 7      return 0;
	 8  }

$ gcc -O0 -g3 test.c -o test

Before patch (step to line 7):
>>> info all-registers fpsr
fpsr           0x10                16
>>> info all-registers fpcr
fpcr           0x0                 0

After patch:
>>> info all-registers fpsr
fpsr           0x10                [ IXC ]
>>> info all-registers fpcr
fpcr           0x0                 [ RMode=0 ]

OK for master ?

gdb/ChangeLog:

2020-11-25  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
	* features/aarch64-fpu.xml: Add named FPCR and FPSR register bit-fields.