Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register.

[John Baldwin <jhb@FreeBSD.org>]

On 9/20/18 2:51 PM, Andrew Burgess wrote:
> * John Baldwin <jhb@FreeBSD.org> [2018-09-20 13:31:46 -0700]:
>> @@ -426,7 +420,22 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
>>  {
>>    if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
>>      {
>> -      if (riscv_has_feature (gdbarch, 'C'))
>> +      enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> 
> byte_order is unused.

Will fix.

>> +      gdb_byte buf[1];
>> +      int status;
>> +
>> +      /* Read the opcode byte to determine the instruction length.  */
>> +      status = target_read_memory (*pcptr, buf, 1);
> 
> This should use target_read_code.  I know that we already have some
> (incorrect) uses of target_read_memory in riscv-tdep.c, but we can fix
> those later.

Ok.

> However, this causes a testsuite regression for gdb.gdb/unittest.exp.
> You can easily reproduce the issue with:
> 
>     (gdb) maintenance selftest 
> 
> We probably need to add a riscv specific case into
> disasm-selftest.c:print_one_insn_test, lots of other targets already
> do.

Ok.  I'll reproduce that and figure out the fix and include it in a V2
patch.

One other question is if I drop the change to default MISA to 0, we should
perhaps fix the comment above riscv_read_misa?  The comment implies that
it falls back to zero if it can't read the register and it does that for
the !target_has_registers case already.  It's not clear from the comment
that targets are required to provide MISA.

-- 
John Baldwin