From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 57044 invoked by alias); 20 Sep 2018 23:01:09 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 57031 invoked by uid 89); 20 Sep 2018 23:01:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_SOFTFAIL autolearn=no version=3.3.2 spammy=Hx-languages-length:1689, burgess, Burgess X-HELO: mail.baldwin.cx Received: from bigwig.baldwin.cx (HELO mail.baldwin.cx) (96.47.65.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 20 Sep 2018 23:01:07 +0000 Received: from John-Baldwins-MacBook-Pro-2.local (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id 6072310A87D; Thu, 20 Sep 2018 19:01:05 -0400 (EDT) Subject: Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register. To: Andrew Burgess References: <20180919231950.22634-1-jhb@FreeBSD.org> <20180919231950.22634-3-jhb@FreeBSD.org> <0081bdf8-04cb-f6b7-d80a-d9a878d0a3ab@FreeBSD.org> <20180920215146.GW5952@embecosm.com> Cc: Jim Wilson , gdb-patches@sourceware.org, Palmer Dabbelt From: John Baldwin Message-ID: <4e2b6d40-dc15-6caa-8520-90289ce972da@FreeBSD.org> Date: Thu, 20 Sep 2018 23:01:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180920215146.GW5952@embecosm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2018-09/txt/msg00745.txt.bz2 On 9/20/18 2:51 PM, Andrew Burgess wrote: > * John Baldwin [2018-09-20 13:31:46 -0700]: >> @@ -426,7 +420,22 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) >> { >> if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) >> { >> - if (riscv_has_feature (gdbarch, 'C')) >> + enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); > > byte_order is unused. Will fix. >> + gdb_byte buf[1]; >> + int status; >> + >> + /* Read the opcode byte to determine the instruction length. */ >> + status = target_read_memory (*pcptr, buf, 1); > > This should use target_read_code. I know that we already have some > (incorrect) uses of target_read_memory in riscv-tdep.c, but we can fix > those later. Ok. > However, this causes a testsuite regression for gdb.gdb/unittest.exp. > You can easily reproduce the issue with: > > (gdb) maintenance selftest > > We probably need to add a riscv specific case into > disasm-selftest.c:print_one_insn_test, lots of other targets already > do. Ok. I'll reproduce that and figure out the fix and include it in a V2 patch. One other question is if I drop the change to default MISA to 0, we should perhaps fix the comment above riscv_read_misa? The comment implies that it falls back to zero if it can't read the register and it does that for the !target_has_registers case already. It's not clear from the comment that targets are required to provide MISA. -- John Baldwin                                                                            Â